Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 154  2011-2013 Microchip Technology Inc.
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC
URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: HC = Hardware Clearable bit
HS = Hardware Settable bit C = Clearable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14 UTXINV: IrDA
®
Encoder Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle ‘0’
0 = UxTX Idle ‘1’
If IREN =
1:
1 = UxTX Idle ‘1’
0 = UxTX Idle ‘0’
bit 12 Unimplemented: Read as ‘0’
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits; followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: UARTx Transmit Enable bit
1 = Transmit is enabled; UxTX pin is controlled by UARTx
0 = Transmit is disabled; any pending transmission is aborted and the buffer is reset. UxTX pin is
controlled by the PORT register.
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and the transmit buffer is empty (the last transmission has
completed)
0 = Transmit Shift Register is not empty; a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on the RSR transfer, making the receive buffer full (i.e., has 2 data characters)
10 = Reserved
01 = Reserved
00 = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters