Datasheet

 2011-2013 Microchip Technology Inc. DS30001037C-page 147
PIC24F16KL402 FAMILY
REGISTER 17-10: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — —SDO2DIS
(1)
SCK2DIS
(1)
SDO1DIS SCK1DIS
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11 SDO2DIS: MSSP2 SDO2 Pin Disable bit
(1)
1 = The SPI output data (SDO2) of MSSP2 to the pin is disabled
0 = The SPI output data (SDO2) of MSSP2 is output to the pin
bit 10 SCK2DIS: MSSP2 SCK2 Pin Disable bit
(1)
1 = The SPI clock (SCK2) of MSSP2 to the pin is disabled
0 = The SPI clock (SCK2) of MSSP2 is output to the pin
bit 9 SDO1DIS: MSSP1 SDO1 Pin Disable bit
1 = The SPI output data (SDO1) of MSSP1 to the pin is disabled
0 = The SPI output data (SDO1) of MSSP1 is output to the pin
bit 8 SCK1DIS: MSSP1 SCK1 Pin Disable bit
1 = The SPI clock (SCK1) of MSSP1 to the pin is disabled
0 = The SPI clock (SCK1) of MSSP1 is output to the pin
bit 7-0 Unimplemented: Read as ‘0’
Note 1: These bits are implemented only on PIC24FXXKL40X/30X devices.