Datasheet

 2011-2013 Microchip Technology Inc. DS30001037C-page 133
PIC24F16KL402 FAMILY
REGISTER 16-6: CCPTMRS0: CCP TIMER SELECT CONTROL REGISTER 0
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
— C3TSEL0 — — C2TSEL0 — — C1TSEL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6 C3TSEL0: CCP3 Timer Selection bit
1 = CCP3 uses TMR3/TMR4
0 = CCP3 uses TMR3/TMR2
bit 5-4 Unimplemented: Read as ‘0’
bit 3 C2TSEL0: CCP2 Timer Selection bit
1 = CCP2 uses TMR3/TMR4
0 = CCP2 uses TMR3/TMR2
bit 2-1 Unimplemented: Read as ‘0’
bit 0 C1TSEL0: CCP1/ECCP1 Timer Selection bit
1 = CCP1/ECCP1 uses TMR3/TMR4
0 = CCP1/ECCP1 uses TMR3/TMR2
Note 1: This register is unimplemented on PIC24FXXKL20X/10X devices; maintain as ‘0’.