Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 128  2011-2013 Microchip Technology Inc.
REGISTER 16-1: CCPxCON: CCPx CONTROL REGISTER (STANDARD CCP MODULES)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DCxB1 DCxB0 CCPxM3
(1)
CCPxM2
(1)
CCPxM1
(1)
CCPxM0
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-4 DCxB<1:0>: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module bits
Capture and
Compare modes:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCxB<9:2>) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits
(1)
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 =PWM mode
1011 = Compare mode: Special Event Trigger; resets timer on CCPx match
(CCPxIF bit is set)
1010 = Compare mode: Generates software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1001 = Compare mode: Initializes CCPx pin high; on compare match, forces CCPx pin low (CCPxIF
bit is set)
1000 = Compare mode: Initializes CCPx pin low; on compare match, forces CCPx pin high (CCPxIF bit is
set)
0111 = Capture mode: Every 16th rising edge
0110 = Capture mode: Every 4th rising edge
0101 = Capture mode: Every rising edge
0100 = Capture mode: Every falling edge
0011 = Reserved
0010 = Compare mode: Toggles output on match (CCPxIF bit is set)
0001 = Reserved
0000 = Capture/Compare/PWM is disabled (resets CCPx module)
Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start the A/D conversion on a CCPx match.