Datasheet

PIC24F16KA102 FAMILY
DS39927C-page 68  2008-2011 Microchip Technology Inc.
REGISTER 8-2: CORCON: CPU CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0
— — — —IPL3
(2)
PSV
(1)
— —
bit 7 bit 0
Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 IPL3: CPU Interrupt Priority Level Status bit
(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 1-0 Unimplemented: Read as ‘0’
Note 1: See Register 3-2 for the description of this bit, which is not dedicated to interrupt control functions.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
Note: Bit 2 is described in Section 3.0 “CPU”.