Datasheet
PIC24F16KA102 FAMILY
DS39927C-page 40 2008-2011 Microchip Technology Inc.
TABLE 4-20: CLOCK CONTROL REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
RCON 0740 TRAPR IOPUWR SBOREN
— — DPSLP — PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1)
OSCCON 0742
— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK
—
LOCK
—CF— SOSCEN OSWEN (Note 2)
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0
— — — — — — — — 3140
OSCTUN 0748
— — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000
REFOCON 074E ROEN
— ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000
HLVDCON 0756 HLVDEN
—HLSIDL— — — — — VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
TABLE 4-21: DEEP SLEEP REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
(1)
DSCON 0758 DSEN — — — — — — — — — — — — — DSBOR RELEASE 0000
DSWAKE 075A
— — — — — — —DSINT0DSFLT — — DSWDT DSRTCC DSMCLR — DSPOR 0000
DSGPR0 075C Deep Sleep General Purpose Register 0
0000
DSGPR1 075E Deep Sleep General Purpose Register 1
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The Deep Sleep registers are only reset on a V
DD POR event.
TABLE 4-22: NVM REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
NVMCON 0760 WR WREN WRERR PGMONLY
— — — — — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000
(1)
NVMKEY 0766 — — — — — — — — NVMKEY7 NVMKEY6 NVMKEY5 NVMKEY4 NVMKEY3 NVMKEY2 NVMKEY1 NVMKEY0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-23: PMD REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
PMD1 0770
— —
T3MD T2MD T1MD
— — — I2C1MD U2MD U1MD
—
SPI1MD
— —ADC1MD0000
PMD2 0772
— — — — — — —IC1MD— — — — — — —OC1MD0000
PMD3 0774
— — — — — CMPMD RTCCMD —CRCPMD — — — — — — — 0000
PMD4 0776
— — — — — — — — — — — EEMD REFOMD CTMUMD HLVDMD — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.