Datasheet

PIC24F16KA102 FAMILY
DS39927C-page 234  2008-2011 Microchip Technology Inc.
TABLE 29-22: AC SPECIFICATIONS
TABLE 29-23: A/D CONVERSION TIMING REQUIREMENTS
(1)
Symbol Characteristics Min Typ Max Units
T
LW BCLKx High Time 20 TCY/2 —ns
T
HW BCLKx Low Time 20 (TCY * BRGx) + TCY/2 —ns
TBLD BCLKx Falling Edge Delay from UxTX -50 — 50 ns
T
BHD BCLKx Rising Edge Delay from UxTX TCY/2 – 50 — TCY/2 + 50 ns
T
WAK Min. Low on UxRX Line to Cause Wake-up — 1 — s
T
CTS Min. Low on UxCTS Line to Start
Transmission
TCY ——ns
T
SETUP Start bit Falling Edge to System Clock Rising
Edge Setup Time
3 ——ns
T
STDELAY Maximum Delay in the Detection of the
Start bit Falling Edge
——TCY + TSETUP ns
A/D CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  T
A  +85°C for Industrial
-40°C  T
A  +125°C for Extended
Param
No.
Symbol Characteristic Min. Typ Max. Units Conditions
Clock Parameters
AD50 T
AD A/D Clock Period 75 — — ns TCY = 75 ns, AD1CON3
is in the default state
AD51 T
RC A/D Internal RC Oscillator Period — 250 — ns
Conversion Rate
AD55 T
CONV Conversion Time — 12 — TAD
AD56 FCNV Throughput Rate — — 500 ksps AVDD  2.7V
AD57 T
SAMP Sample Time — 1 — TAD
AD58 TACQ Acquisition Time 750 — — ns (Note 2)
AD59 TSWC Switching Time from Convert to
Sample
——(Note 3)
AD60 T
DIS Discharge Time 0.5 — — TAD
Clock Parameters
AD61 T
PSS Sample Start Delay from Setting
Sample bit (SAMP)
2— 3 TAD
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD).
3: On the following cycle of the device clock.