Datasheet
2008-2011 Microchip Technology Inc. DS39927C-page 143
PIC24F16KA102 FAMILY
bit 5 ACKDT: Acknowledge Data bit (when operating as I
2
C master; applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(when operating as I
2
C master; applicable during master receive)
1 = Initiates Acknowledge sequence on SDA1 and SCL1 pins and transmits ACKDT data bit; hardware
is clear at the end of the master Acknowledge sequence
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I
2
C master)
1 = Enables Receive mode for I
2
C; hardware is clear at the end of eighth bit of master receive data byte
0 = Receive sequence not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I
2
C master)
1 = Initiates Stop condition on SDA1 and SCL1 pins; hardware is clear at end of master Stop sequence
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I
2
C master)
1 = Initiates Repeated Start condition on SDA1 and SCL1 pins; hardware is clear at end of master
Repeated Start sequence
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I
2
C master)
1 = Initiates Start condition on SDA1 and SCL1 pins; hardware is clear at end of master Start sequence
0 = Start condition is not in progress
REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER (CONTINUED)