Datasheet

PIC24F16KA102 FAMILY
DS39927C-page 134  2008-2011 Microchip Technology Inc.
REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC
SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0
bit 15 bit 8
R-0,HSC R/C-0, HS R/W-0, HSC R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC
SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’ HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit H = Hardware Settable bit C = Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SPIEN: SPI1 Enable bit
1 = Enables module and configures SCK1, SDO1, SDI1 and SS1
as serial port pins
0 = Disables module
bit 14 Unimplemented: Read as ‘0’
bit 13 SPISIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 SPIBEC<2:0>: SPI1 Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers are pending.
Slave mode:
Number of SPI transfers are unread.
bit 7 SRMPT: Shift Register (SPI1SR) Empty bit (valid in Enhanced Buffer mode)
1 = SPI1 Shift register is empty and ready to send or receive
0 = SPI1 Shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded
The user software has not read the previous data in the SPI1BUF register.
0 = No overflow has occurred
bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
bit 4-2 SISEL<2:0>: SPI1 Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPI1 transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPI1SR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPI1SR; now the transmit is complete
100 = Interrupt when one data byte is shifted into the SPI1SR; as a result, the TX FIFO has one open spot
011 = Interrupt when the SPI1 receive buffer is full (SPIRBF bit set)
010 = Interrupt when the SPI1 receive buffer is 3/4 or more full
001 = Interrupt when data is available in receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty
(SRXMPT bit is set)