PIC24F16KL402 FAMILY Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with XLP Technology Power Management Modes: Peripheral Features: • • • • • • High-Current Sink/Source (18 mA/18 mA) on All I/O Pins • Configurable Open-Drain Outputs on Digital I/O Pins • Up to Three External Interrupt Sources • Two 16-Bit Timer/Counters with Selectable Clock Sources • Up to Two 8-Bit Timers/Counters with Programmable Prescalers • Two Capture/Compare/PWM (CCP) modules: - Modules automatically configur
PIC24F16KL402 FAMILY Analog Features: • 10-Bit, up to 12-Channel Analog-to-Digital (A/D) Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Rail-to-Rail Analog Comparators with Programmable Input/Output Configuration • On-Chip Voltage Reference Special Microcontroller Features: • Operating Voltage Range of 1.8V to 3.
PIC24F16KL402 FAMILY Pin Diagrams: PIC24FXXKL302/402 28-Pin QFN(1) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS AN9/T3CK/REFO/SS1/CN11/RB15 CVREF/AN10/C1OUT/FLT0/INT1/CN12/RB14 AN11/SDO1/CN13/RB13 AN12/HLVDIN/SS2/CCP2/CN14/RB12 PGEC2/SCK1/P1C/CN15/RB11 PGED2/SDI1/P1B/CN16/RB10 C2OUT/CCP1/P1A/INT2/CN8/RA6 SDI2/CCP3/CN9/RA7 SDA1/T1CK/U1RTS/P1D/CN21/RB9 SCL1/U1CTS/CN22/RB8 U1TX/INT0/CN23/RB7 PGEC3/ASCL1(2)/SDO2/CN24/RB6 28 27 26 25 24 23 22 1 2 3 PIC24FXXKL302(2) 4 PIC24FXXKL402 5 6 7 8 9 10 11 12 13
PIC24F16KL402 FAMILY Pin Diagrams: PIC24FXXKL301/401 20-Pin QFN(1) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD VSS AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15 CVREF/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14 AN11/SDO1/P1D/CN13/RB13 AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12 C2OUT/CCP1/P1A/INT2/CN8/RA6 SDA1/T1CK/U1RTS/CCP3/CN21/RB9 SCL1/U1CTS/SS1/CN22/RB8 U1TX/INT0/CN23/RB7 PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1 PGEC2/VREF+/CVREF+/AN0/SDA2/SDI2/CN2/RA0 MCLR/VPP/RA5 VDD VSS MCLR/VPP/RA5 PGEC2/VREF+/CVREF+/AN0/SDA2/SDI2
PIC24F16KL402 FAMILY Pin Diagrams: PIC24FXXKL10X/20X PGED2/CVREF-/VREF-/AN1/CN3/RA1 PGEC2/VREF+/CVREF+/AN0/CN2/RA0 MCLR/VPP/RA5 VDD VSS 20-Pin QFN(1) 20 19 18 17 16 PGED1/AN2/ULPWU/C1IND/CN4/RB0 PGEC1/AN3/C1INC/CN5/RB1 AN4/T3G/U1RX/CN6/RB2 OSCI/AN13/C1INB/CLKI/CN30/RA2 OSCO/AN14/C1INA/CLKO/CN29/RA3 15 1 14 2 PIC24FXXKL101(2) 13 3 PIC24FXXKL201 12 4 11 5 AN9/T3CK/REFO/CN11/RB15 CVREF/AN10/SDI1/C1OUT/INT1/CN12/RB14 AN11/SDO1/CN13/RB13 AN12/HLVDIN/SCK1/CCP2/CN14/RB12 CCP1/INT2/CN8/RA6 PGED3/SOSCI/AN15/CN1
PIC24F16KL402 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 21 3.0 CPU ....................................................................................................
PIC24F16KL402 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 8 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24F04KL100 • PIC24F04KL101 • PIC24F08KL200 • PIC24F08KL201 • PIC24F08KL301 • PIC24F08KL302 • PIC24F08KL401 • PIC24F16KL401 • PIC24F08KL402 • PIC24F16KL402 The PIC24F16KL402 family adds an entire range of economical, low pin count and low-power devices to Microchip’s portfolio of 16-bit microcontrollers.
PIC24F16KL402 FAMILY 1.2 Other Special Features 1.3 • Communications: The PIC24F16KL402 family incorporates multiple serial communication peripherals to handle a range of application requirements. The MSSP module implements both SPI and I2C™ protocols, and supports both Master and Slave modes of operation for each. Devices also include one of two UARTs with built-in IrDA® encoders/decoders. • Analog Features: Select members of the PIC24F16KL402 family include a 10-bit A/D Converter module.
PIC24F16KL402 FAMILY PIC24F08KL302 PIC24F08KL401 PIC24F08KL301 Program Memory (bytes) 16K 8K 8K 16K 8K 8K Program Memory (instructions) 5632 2816 2816 5632 2816 2816 Data Memory (bytes) 1024 1024 1024 1024 1024 1024 Data EEPROM Memory (bytes) 512 512 256 512 512 256 31 (27/4) 31 (27/4) 30 (26/4) 31 (27/4) 31 (27/4) 30 (26/4) Features Operating Frequency Interrupt Sources (soft vectors/NMI traps) DC – 32 MHz I/O Ports PORTA<7:0> PORTB<15:0> Total I/O Pins Timers (8/
PIC24F16KL402 FAMILY PIC24F04KL101 PIC24F08KL200 PIC24F04KL100 DEVICE FEATURES FOR THE PIC24F16KL20X/10X DEVICES PIC24F08KL201 TABLE 1-3: 8K 4K 8K 4K Program Memory (instructions) 2816 1408 2816 1408 Data Memory (bytes) 512 512 512 512 — — — — 27 (23/4) 26 (22/4) 27 (23/4) 26 (22/4) Features Operating Frequency Program Memory (bytes) Data EEPROM Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports DC – 32 MHz PORTA<6:0> PORTB<15:12,9:7,4,2:0> Total I/O Pins Tim
PIC24F16KL402 FAMILY FIGURE 1-1: PIC24F16KL402 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller 16 8 16 16 Data Latch PSV and Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTA(1) RA<0:7> 16 23 16 Read AGU Write AGU Address Latch Program Memory Data EEPROM Data Latch 16 EA MUX 24 Inst Latch Literal Data Address Bus 16 16 PORTB(1) RB<0:15> Inst Register Instruction Decode and Control Control Signa
PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin PDIP/ SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN I/O Buffer Description 2 19 2 27 I ANA AN1 3 20 3 28 I ANA A/D Analog Inputs. Not available on PIC24F16KL30X family devices.
PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin PDIP/ SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN I/O Buffer CN0 10 7 12 9 I ST CN1 9 6 11 8 I ST CN2 2 19 2 27 I ST CN3 3 20 3 28 I ST CN4 4 1 4 1 I ST CN5 5 2 5 2 I ST CN6 6 3 6 3 I ST Function CN7 — — 7 4 I ST CN8 14 11 20 17 I ST CN9 — — 19 16 I ST CN11 18 15 26 23 I ST CN12 17 14 25 22 I ST CN
PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 20-Pin PDIP/ SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN I/O Buffer Description PGEC1 5 2 5 2 I/O ST ICSP™ Clock 1 PCED1 4 1 4 1 I/O ST ICSP Data 1 PGEC2 2 19 22 19 I/O ST ICSP Clock 2 PGED2 3 20 21 18 I/O ST ICSP Data 2 PGEC3 10 7 15 12 I/O ST ICSP Clock 3 PGED3 9 6 14 11 I/O ST ICSP Data 3 RA0 2 19 2 27 I/O ST PORTA Pins
PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 20-Pin PDIP/ SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN I/O Buffer Description SOSCI 9 6 11 8 I ANA Secondary Oscillator Input SOSCO 10 7 12 9 O ANA Secondary Oscillator Output SS1 12 9 26 23 O — SPI1 Slave Select SS2 15 12 23 20 O — SPI2 Slave Select T1CK 13 10 18 15 I ST Timer1 Clock T3CK 18 15 26 23 I ST Timer3 Clock T3G 6
PIC24F16KL402 FAMILY TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin PDIP/ SSOP/ SOIC 20-Pin QFN 14-Pin PDIP/ TSSOP I/O Buffer 2 19 2 I ANA AN1 3 20 3 I ANA AN2 4 1 — I ANA AN3 5 2 — I ANA ANA Function AN0 Description A/D Analog Inputs. Not available on PIC24F16KL10X family devices.
PIC24F16KL402 FAMILY TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin PDIP/ SSOP/ SOIC 20-Pin QFN 14-Pin PDIP/ TSSOP I/O Buffer CVREF 17 14 11 I ANA Comparator Voltage Reference Output CVREF+ 2 19 2 I ANA Comparator Reference Positive Input Voltage CVREF- 3 20 3 I ANA Comparator Reference Negative Input Voltage HLVDIN 15 12 6 I ST High/Low-Voltage Detect Input INT0 11 8 12 I ST Interrupt 0 Input INT1 17 14 11 I ST Interrupt
PIC24F16KL402 FAMILY TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin PDIP/ SSOP/ SOIC 20-Pin QFN 14-Pin PDIP/ TSSOP I/O SCK1 15 12 8 I/O ST MSSP1 SPI Serial Input/Output Clock SCL1 12 9 8 I/O I2C MSSP1 I2C Clock Input/Output SCLKI 10 7 12 I ST Digital Secondary Clock Input I/O 2 I C MSSP1 I2C Data Input/Output Function SDA1 13 10 9 Buffer Description SDI1 17 14 11 I ST MSSP1 SPI Serial Data Input SDO1 16 13 9 O — MSSP1 S
PIC24F16KL402 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(1) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.
PIC24F16KL402 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24F16KL402 FAMILY 2.4 ICSP Pins FIGURE 2-3: The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω.
PIC24F16KL402 FAMILY For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” DS30001037C-page 24 2.
PIC24F16KL402 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the CPU, refer to the “dsPIC33/PIC24 Family Reference Manual”, “CPU” (DS39703). The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field.
PIC24F16KL402 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCL PCH Program Counter Loop Stack Control Control Logic Logic 23 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory EA MUX Address Bus Data Latch ROM Latch 24 16 Instruction Decode and Control Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support 16 Literal Data Data EEPROM 1
PIC24F16KL402 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL — — — — — — — DC IPL RA N OV Z C 2 1 0 15 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register REPEAT Loop Counter Regis
PIC24F16KL402 FAMILY 3.
PIC24F16KL402 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0 — — — — IPL3(1) PSV — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priori
PIC24F16KL402 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1.
PIC24F16KL402 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, the PIC24F microcontrollers feature separate program and data memory space and bussing. This architecture also allows the direct access of program memory from the data space during code execution. 4.1 Program Address Space User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh).
PIC24F16KL402 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In the PIC24F16KL402 family, the data EEPROM is mapped to the top of the user program memory space, starting at address, 7FFE00, and expanding up to address, 7FFFFF. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented.
PIC24F16KL402 FAMILY 4.2 Data Address Space The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs); one each for read and write operations. The data space memory map is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words.
PIC24F16KL402 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address (EA) calculations are internally scaled to step through word-aligned memory.
File Name Start Addr CPU CORE REGISTERS MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 0000 WREG4 0008 Working Register 4 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Regi
2011-2013 Microchip Technology Inc.
File Name Addr INTERRUPT CONTROLLER REGISTER MAP Bit 15 INTCON1 0080 NSTDIS Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 All Resets 2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc.
File Name MSSP REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets SSP1BUF 0200 — — — — — — — — SSP1CON1 0202 — — — — — — — — WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 SSP1CON2 0204 — — — — — — — — GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 SSP1CON3 0206 — — — — — — — — ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 SMP CKE D/A
2011-2013 Microchip Technology Inc.
File Name Addr A/D REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ADC1BUF0 0300 A/D Buffer 0 xxxx ADC1BUF1 0302 A/D Buffer 1 xxxx AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000 AD1CON2 0322 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — — r — SMPI3 SMPI2 SMPI1 SMPI0 r ALTS 0000 AD1CON3 0324 ADRC AD1CHS 0328 CH0NB — — AD1CSSL 0330
2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 4.2.5 SOFTWARE STACK 4.3 In addition to its use as a Working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.
PIC24F16KL402 FAMILY TABLE 4-20: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 2: 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0>(2) Data EA<14:0
PIC24F16KL402 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY AND DATA EEPROM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. It also offers a direct method of reading or writing a word of any address within data EEPROM memory. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.
PIC24F16KL402 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into a 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the MSb of the data space EA is ‘1’ and PSV is enabled by setting the PSV bit in the CPU Control (CORCON<2>) register.
PIC24F16KL402 FAMILY 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Flash Programming, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Program Memory” (DS39715). The PIC24F16KL402 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with VDD over 1.8V.
PIC24F16KL402 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time, and to program one row at a time. The 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks and single row write block (96 bytes) are edge-aligned, from the beginning of program memory.
PIC24F16KL402 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY(4) — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5(1) NVMOP4(1) NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1) bit 7 bit 0 Legend: SO = Settable Only bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, re
PIC24F16KL402 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is as follows: 1. 2. 3. Read a row of program memory (32 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase a row (see Example 5-1): a) Set the NVMOPx bits (NVMCON<5:0>) to ‘011000’ to configure for row erase.
PIC24F16KL402 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE // C example using MPLAB C30 int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Global variable located in Pgm Memory unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); offset = &progAddr & 0xFFFF; // Initialize PM Page Boundary SFR // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // wi
PIC24F16KL402 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Global variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write //Set up NVMCON for row programming NVMCON = 0x4004; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = __buil
PIC24F16KL402 FAMILY 6.0 Note: DATA EEPROM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Data EEPROM, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Data EEPROM” (DS39720). The data EEPROM memory is a Nonvolatile Memory (NVM), separate from the program and volatile data RAM.
PIC24F16KL402 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5(1) NVMOP4(1) NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit SO = Settable Only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
PIC24F16KL402 FAMILY 6.3 NVM Address Register 6.4 As with Flash program memory, the NVM Address Registers, NVMADRU and NVMADR, form the 24-bit Effective Address (EA) of the selected row or word for data EEPROM operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA.
PIC24F16KL402 FAMILY 6.4.1 ERASE DATA EEPROM A typical erase sequence is provided in Example 6-2. This example shows how to do a one-word erase. Similarly, a four-word erase and an eight-word erase can be done. This example uses C library procedures to manage the Table Pointer (builtin_tblpage and builtin_tbloffset) and the Erase Page Pointer (builtin_tblwtl). The memory unlock sequence (builtin_write_NVM) also sets the WR bit to initiate the operation and returns control when complete.
PIC24F16KL402 FAMILY 6.4.1.1 Data EEPROM Bulk Erase 6.4.2 SINGLE-WORD WRITE To erase the entire data EEPROM (bulk erase), the address registers do not need to be configured because this operation affects the entire data EEPROM. The following sequence helps in performing a bulk erase: To write a single word in the data EEPROM, the following sequence must be followed: 1. 2. 2. 3. 4. 5. Configure NVMCON to Bulk Erase mode. Clear the NVMIF status bit and enable the NVM interrupt (optional).
PIC24F16KL402 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the Table Read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location followed by a TBLRDL instruction.
PIC24F16KL402 FAMILY 7.0 RESETS Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Resets, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Reset with Programmable Brown-out Reset” (DS39728). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24F16KL402 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 7-1: R/W-0 R/W-0 R/W-0(3) U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR SBOREN — — — CM PMSLP bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflic
PIC24F16KL402 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 7-1: bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set after a POR) 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has
PIC24F16KL402 FAMILY 7.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 7-3. Note that the System Reset Signal, SYSRST, is released after the POR and PWRT delay times expire. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released.
PIC24F16KL402 FAMILY 7.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24F16KL402 FAMILY 7.4.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON<1>) is always reset to ‘1’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘0’ in the software, immediately after any POR event.
PIC24F16KL402 FAMILY 8.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Interrupt Controller, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU.
PIC24F16KL402 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vec
PIC24F16KL402 FAMILY TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h Reserved 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector Number IVT Address ADC1 Conversion Done 13 00002Eh Compa
PIC24F16KL402 FAMILY 8.3 Interrupt Control and Status Registers Depending on the particular device, the PIC24F16KL402 family of devices implements up to 28 registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0 through IFS5 IEC0 through IEC5 IPC0 through IPC7, ICP9, IPC12, ICP16, ICP18 and IPC20 • INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2.
PIC24F16KL402 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘0’ bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status b
PIC24F16KL402 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0 — — — — IPL3(2) PSV(1) — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU Interrupt Pri
PIC24F16KL402 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting i
PIC24F16KL402 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Us
PIC24F16KL402 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 NVMIF — AD1IF U1TXIF U1RXIF — — T3IF bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 T2IF CCP2IF — — T1IF CCP1IF — INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NVMIF: NVM Interrupt Flag Status bit 1 = Interrupt
PIC24F16KL402 FAMILY REGISTER 8-6: R/W-0 U2TXIF(1) bit 15 IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 U2RXIF(1) R/W-0 INT2IF U-0 — R/W-0 T4IF(1) U-0 — R/W-0 CCP3IF(1) bit 8 U-0 — U-0 — U-0 — R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 BCL1IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 SSP1IF bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ =
PIC24F16KL402 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — T3GIF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 T3GIF: Timer3 External Gate Interrupt Flag Status bit 1 = Interrupt request has occurred
PIC24F16KL402 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — HLVDIF bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 R/W-0 R/W-0 U-0 — U2ERIF(1) U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘0’ bit 8 HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt r
PIC24F16KL402 FAMILY REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 NVMIE — AD1IE U1TXIE U1RXIE — — T3IE bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 T2IE CCP2IE — — T1IE CCP1IE — INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NVMIE: NVM Interrupt Enable bit 1 = Interrupt request is enabled 0
PIC24F16KL402 FAMILY REGISTER 8-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U2TXIE(1) U2RXIE(1) INT2IE — T4IE(1) — CCP3IE(1) — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE CMIE BCL1IE SSP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit(1) 1
PIC24F16KL402 FAMILY REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — T3GIE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 T3GIF: Timer3 External Gate Interrupt Enable bit 1 = Interrupt request is enabled 0 =
PIC24F16KL402 FAMILY REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — HLVDIE bit 15 bit 8 U-0 U-0 — — U-0 — U-0 U-0 — — R/W-0 U2ERIE (1) R/W-0 U-0 U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘0’ bit 8 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Interrupt
PIC24F16KL402 FAMILY REGISTER 8-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — CCP1IP2 CCP1IP1 CCP1IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Int
PIC24F16KL402 FAMILY REGISTER 8-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — CCP2IP2 CCP2IP1 CCP2IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111
PIC24F16KL402 FAMILY REGISTER 8-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1RXIP2 U1RXIP1 U1RXIP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priorit
PIC24F16KL402 FAMILY REGISTER 8-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP<2:0>: NVM Inter
PIC24F16KL402 FAMILY REGISTER 8-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — BCL1IP2 BCL1IP1 BCL1IP0 — SSP1IP2 SSP1IP1 SSP1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNI
PIC24F16KL402 FAMILY REGISTER 8-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt
PIC24F16KL402 FAMILY REGISTER 8-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T4IP2(1) T4IP1(1) T4IP0(1) — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CCP3IP2(1) CCP3IP1(1) CCP3IP0(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt
PIC24F16KL402 FAMILY REGISTER 8-24: U-0 — IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-1 U2TXIP2 R/W-0 (1) U2TXIP1 R/W-0 (1) U2TXIP0 U-0 (1) — R/W-1 R/W-0 (1) U2RXIP2 U2RXIP1 R/W-0 (1) U2RXIP0(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT2IP2 INT2IP1 INT2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24F16KL402 FAMILY REGISTER 8-25: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T3GIP2 T3GIP1 T3GIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 T3GIP<2:0>: Timer3 External Gate Interrupt Priority bits 111 = Int
PIC24F16KL402 FAMILY REGISTER 8-26: U-0 IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 — — U-0 U-0 — — U-0 — R/W-1 BCL2IP2 R/W-0 (1) BCL2IP1 R/W-0 (1) BCL2IP0(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SSP2IP2(1) SSP2IP1(1) SSP2IP0(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 BCL2IP<2:0>: MSSP2
PIC24F16KL402 FAMILY REGISTER 8-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — U2ERIP2(1) U2ERIP1(1) U2ERIP0(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2(1) U1ERIP1(1) U1ERIP0(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP<2:0>: UART
PIC24F16KL402 FAMILY REGISTER 8-28: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits
PIC24F16KL402 FAMILY REGISTER 8-30: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 r-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ r VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt R
PIC24F16KL402 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and the type of interrupt source.
PIC24F16KL402 FAMILY 9.0 • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC mode. When using an external clock source, the current consumption is reduced by setting the declaration bits to the expected frequency range. • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown.
PIC24F16KL402 FAMILY 9.1 CPU Clocking Scheme 9.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins PIC24F16KL402 family devices consist of two types of secondary oscillators: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC<5>) bit.
PIC24F16KL402 FAMILY 9.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers (SFRs): • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 9-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 9-1: The Clock Divider register (Register 9-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator.
PIC24F16KL402 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enable bit If FSCM is Enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is Disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24F16KL402 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit, an
PIC24F16KL402 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tu
PIC24F16KL402 FAMILY 9.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 9.4.1 The Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits.
PIC24F16KL402 FAMILY The following code sequence for a clock switch is recommended: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8>, in two back-to-back instructions. Write the new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence.
PIC24F16KL402 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 104 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 10.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Power-Saving Features, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Power-Saving Features with Deep Sleep” (DS39727). The PIC24F16KL402 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
PIC24F16KL402 FAMILY 10.2.1 SLEEP MODE 10.2.2 IDLE MODE Sleep mode includes these features: Idle mode has these features: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. • The device current consumption will be reduced to a minimum, provided that no I/O pin is sourcing current. • The I/O pin directions and states are frozen. • The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled.
PIC24F16KL402 FAMILY 10.3 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on pin, RB0, allows a slow falling voltage to generate an interrupt without excess current consumption. This feature provides a low-power technique for periodically waking up the device from Sleep mode. To use this feature: 1. 2. 3. 4. 5. Charge the capacitor on RB0 by configuring the RB0 pin to an output and setting it to ‘1’. Stop charging the capacitor by configuring RB0 as an input.
PIC24F16KL402 FAMILY REGISTER 10-1: ULPWCON: ULPWU CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 ULPEN — ULPSIDL — — — — ULPSINK bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ULPEN: ULPWU Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplement
PIC24F16KL402 FAMILY 10.4 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted, synchronous communication, even while it is doing nothing else.
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 110 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 11.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the I/O Ports, refer to the “dsPIC33/PIC24 Family Reference Manual”, “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24F16KL402 family devices do not support Peripheral Pin Select features.
PIC24F16KL402 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORTx, LATx and TRISx registers for data control, each port pin can be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 11.1.
PIC24F16KL402 FAMILY REGISTER 11-1: ANSA: PORTA ANALOG SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 ANSA<3:0>: Analog Select Control bits 1 = Digital input buffer is not
PIC24F16KL402 FAMILY 11.3 Input Change Notification The Input Change Notification (ICN) function of the I/O ports allows the PIC24F16KL402 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode, when the clocks are disabled.
PIC24F16KL402 FAMILY 12.0 Figure 12-1 illustrates a block diagram of the 16-bit Timer1 module. TIMER1 Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3.
PIC24F16KL402 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON — TSIDL — — — T1ECS1(1) T1ECS0(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bi
PIC24F16KL402 FAMILY 13.0 This module is controlled through the T2CON register (Register 13-1), which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. TIMER2 MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F16KL402 FAMILY REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Sel
PIC24F16KL402 FAMILY 14.0 • Selectable clock source (internal or external) with device clock, SOSC or LPRC oscillator options • Interrupt-on-overflow • Multiple timer gating options, including: - User-selectable gate sources and polarity - Gate/toggle operation - Single Pulse (One-Shot) mode • Module Reset on ECCP Special Event Trigger TIMER3 MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F16KL402 FAMILY REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC — TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 TMR3CS<1:0>: Timer3 Clock Source Select bits 1
PIC24F16KL402 FAMILY REGISTER 14-2: T3GCON: TIMER3 GATE CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3DONE T3GVAL T3GSS1 T3GSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 TMR3GE: Timer
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 122 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 15.0 The Timer4 module has a control register shown in Register 15-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 is controlled by this register. TIMER4 MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F16KL402 FAMILY REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Sel
PIC24F16KL402 FAMILY 16.0 Note: CAPTURE/COMPARE/PWM (CCP) AND ENHANCED CCP MODULES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Capture/Compare/PWM module, refer to the “dsPIC33/PIC24 Family Reference Manual”. Depending on the particular device, PIC24F16KL402 family devices include up to three CCP and/or ECCP modules.
PIC24F16KL402 FAMILY FIGURE 16-1: GENERIC CAPTURE MODE BLOCK DIAGRAM Set CCPxIF (E)CCPx Pin Prescaler 1, 4, 16 TMR3L CCPRxH CCPRxL and Edge Detect 4 CCPxCON<3:0> 4 Q1:Q4 FIGURE 16-2: TMR3H GENERIC COMPARE MODE BLOCK DIAGRAM CCPRxH Set CCPxIF CCPRxL Special Event Trigger (Timer3 Reset) CCPx Pin Compare Match Comparator TMR3H S Output Logic Q R CCP Output Enable 4 TMR3L CCPxCON<3:0> FIGURE 16-3: SIMPLIFIED PWM BLOCK DIAGRAM CCPxCON<5:4> Duty Cycle Registers CCPRxL CCPRxH (Slav
PIC24F16KL402 FAMILY FIGURE 16-4: SIMPLIFIED BLOCK DIAGRAM OF ENHANCED PWM MODE DC1B<1:0> Duty Cycle Registers PM<1:0> CCPR1L 4 2 CCP1M<3:0> ECCP1/P1A ECCP1/P1A Output ECCP Enable CCPR1H (Slave) P1B Comparator R Q Output Controller P1B Output ECCP Enable P1C Output P1C TMR2(2) (1) ECCP Enable S P1D Output P1D Comparator Clear Timer, CCP1 Pin and Latch D.C.
PIC24F16KL402 FAMILY REGISTER 16-1: CCPxCON: CCPx CONTROL REGISTER (STANDARD CCP MODULES) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 DCxB1 R/W-0 DCxB0 R/W-0 CCPxM3 R/W-0 (1) R/W-0 (1) CCPxM2 CCPxM1 R/W-0 (1) CCPxM0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<
PIC24F16KL402 FAMILY REGISTER 16-2: CCP1CON: ECCP1 CONTROL REGISTER (ECCP MODULES ONLY)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 PM1 PM0 R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 (2) CCP1M2 R/W-0 (2) CCP1M1 R/W-0 (2) CCP1M0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7
PIC24F16KL402 FAMILY ECCP1AS: ECCP1 AUTO-SHUTDOWN CONTROL REGISTER(1) REGISTER 16-3: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ECCPA
PIC24F16KL402 FAMILY REGISTER 16-4: ECCP1DEL: ECCP1 ENHANCED PWM CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 PRSEN: PWM Restart Enab
PIC24F16KL402 FAMILY PSTR1CON: ECCP1 PULSE STEERING CONTROL REGISTER(1) REGISTER 16-5: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 CMPL<1:0>: Complement
PIC24F16KL402 FAMILY REGISTER 16-6: CCPTMRS0: CCP TIMER SELECT CONTROL REGISTER 0(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 — C3TSEL0 — — C2TSEL0 — — C1TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6 C3TSEL0: CCP3 Timer Selection bit 1 = CCP3 uses TMR3/TMR4 0
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 134 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 17.0 Note: MASTER SYNCHRONOUS SERIAL PORT (MSSP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on MSSP, refer to the “dsPIC33/PIC24 Family Reference Manual”. The Master Synchronous Serial Port (MSSP) module is an 8-bit serial interface, useful for communicating with other peripheral or microcontroller devices.
PIC24F16KL402 FAMILY FIGURE 17-1: MSSPx BLOCK DIAGRAM (SPI MODE) Internal Data Bus Write Read SSPxBUF SDIx SSPxSR bit 0 SDOx SSx Shift Clock SSx Control Enable Edge Select 2 Clock Select SMP:CKE 2 SCKx Edge Select SSPxADD<7:0> SSPM<3:0> 4 TMR2 Output 2 ( ) Prescaler TOSC 4, 16, 64 7 Baud Rate Generator Data to TXx/RXx in SSPxSR TRISx bit Note: FIGURE 17-2: Refer to the device data sheet for pin multiplexing.
PIC24F16KL402 FAMILY FIGURE 17-3: MSSPx BLOCK DIAGRAM (I2C™ MODE) Internal Data Bus Read Write SSPxBUF SCLx Shift Clock SSPxSR SDAx MSb LSb Address Mask Match Detect Address Match SSPxADD Start and Stop bit Detect Note: Set/Reset S, P bits Only port I/O names are shown in this diagram. Refer to the text for a full list of multiplexed functions.
PIC24F16KL402 FAMILY REGISTER 17-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 SMP R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 (1) D/A P S R/W UA BF CKE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SMP: Sample bit SPI Master mode: 1 = Input data is s
PIC24F16KL402 FAMILY REGISTER 17-2: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 SMP CKE R-0 R-0 R-0 R-0 R-0 R-0 D/A P(1) S(1) R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SMP: Slew Rate Control bit In Master or Slave mod
PIC24F16KL402 FAMILY REGISTER 17-2: bit 0 SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) (CONTINUED) BF: Buffer Full Status bit In Transmit mode: 1 = Transmit is in progress, SSPxBUF is full 0 = Transmit is complete, SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: 2: 3: This bit is cleared on RESET and when SSPEN is cleared.
PIC24F16KL402 FAMILY REGISTER 17-3: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 WCOL R/W-0 (1) SSPOV R/W-0 (2) SSPEN R/W-0 CKP R/W-0 SSPM3 (3) R/W-0 SSPM2 (3) R/W-0 SSPM1 (3) R/W-0 SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 WC
PIC24F16KL402 FAMILY REGISTER 17-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 WCOL:
PIC24F16KL402 FAMILY REGISTER 17-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 GCEN:
PIC24F16KL402 FAMILY REGISTER 17-6: SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R/W-0 ACKTIM PCIE R/W-0 SCIE R/W-0 (1) BOEN R/W-0 R/W-0 R/W-0 R/W-0 SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ACKTIM: Acknowledge Ti
PIC24F16KL402 FAMILY REGISTER 17-7: SSPxCON3: MSSPx CONTROL REGISTER 3 (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM(2) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ACKTIM: Acknowledge T
PIC24F16KL402 FAMILY REGISTER 17-8: SSPxADD: MSSPx SLAVE ADDRESS/BAUD RATE GENERATOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 ADD<7:0>: Slave Address/Baud Rate Generator Value bi
PIC24F16KL402 FAMILY REGISTER 17-10: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SDO2DIS(1) SCK2DIS(1) SDO1DIS SCK1DIS bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 SDO2DIS: MSSP2 SDO2 Pin Disable bit(1) 1 = The SPI
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 148 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 18.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Universal Asynchronous Receiver Transmitter, refer to the “dsPIC33/PIC24 Family Reference Manual”, “UART” (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in this PIC24F device family.
PIC24F16KL402 FAMILY 18.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The UxBRG register controls the period of a free-running, 16-bit timer. Equation 18-1 provides the formula for computation of the baud rate with BRGH = 0. EQUATION 18-1: The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 18-2 shows the formula for computation of the baud rate with BRGH = 1.
PIC24F16KL402 FAMILY 18.2 1. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt, two cycles after being set). Write data byte to lower byte of UxTXREG word.
PIC24F16KL402 FAMILY REGISTER 18-1: R/W-0 UxMODE: UARTx MODE REGISTER U-0 UARTEN — R/W-0 USIDL R/W-0 IREN (1) R/W-0 U-0 R/W-0(2) R/W-0(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x =
PIC24F16KL402 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1:
PIC24F16KL402 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 HC = Hardware Clearable bit Legend: HS = Hardware Settable bit C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writab
PIC24F16KL402 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of the received data = 1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at th
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 156 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 19.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 10-Bit High-Speed A/D Converter, refer to the “dsPIC33/PIC24 Family Reference Manual”, “10-Bit A/D Converter” (DS39705). A block diagram of the A/D Converter is displayed in Figure 19-1. To perform an A/D conversion: 1.
PIC24F16KL402 FAMILY FIGURE 19-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD VREF+ VR Select VR+ AVSS 16 VR- VREF- Comparator VINH VINL AN0 S/H VR- VR+ DAC 10-Bit SAR VINH Conversion Logic MUX A AN1 AN2(1) Data Formatting AN3(1) AN1 AN4(1) VINL AN9 ADC1BUF0: ADC1BUF1 AN10 AD1CON1 AD1CON2 (1) AN11 AD1CON3 AN12(1) AD1CHS MUX B AN13 AN14 AN15 AN1 VINH AD1CSSL VINL VBG Sample Control Control Logic Conversion Control Input MUX Control Pin Config Con
PIC24F16KL402 FAMILY REGISTER 19-1: R/W-0 (1) ADON AD1CON1: A/D CONTROL REGISTER 1 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HSC R-0, HSC SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D O
PIC24F16KL402 FAMILY REGISTER 19-2: R/W-0 AD1CON2: A/D CONTROL REGISTER 2 R/W-0 VCFG2 R/W-0 VCFG1 R/W-0 U-0 R/W-0 U-0 U-0 — CSCNA — — (1) VCFG0 OFFCAL bit 15 bit 8 R-x U-0 R/W-0 R/W-0 R/W-0 R/W-0 r-0 R/W-0 r — SMPI3 SMPI2 SMPI1 SMPI0 r ALTS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Voltage Reference Con
PIC24F16KL402 FAMILY REGISTER 19-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D internal
PIC24F16KL402 FAMILY - REGISTER 19-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for MU
PIC24F16KL402 FAMILY REGISTER 19-5: R/W-0 AD1CSSL: A/D INPUT SCAN SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL<15:8>(1) bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL<4:0>(1) — CSSL<7:6> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 CSSL<15:6>: A/D Input Pin Scan Selection bits(1) 1 = Corresponding analog channel selected for input scan
PIC24F16KL402 FAMILY A/D CONVERSION CLOCK PERIOD(1) EQUATION 19-1: ADCS = TAD –1 TCY TAD = TCY • (ADCS + 1) Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. Note 1: FIGURE 19-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA ANx CPIN 6-11 pF (Typical) RIC 250W VT = 0.6V RSS 5 k (Typical) Sampling Switch RSS VT = 0.6V CHOLD = DAC Capacitance = 4.
PIC24F16KL402 FAMILY FIGURE 19-3: A/D TRANSFER FUNCTION Digital Output Code Binary (Decimal) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 166 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 20.0 The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F16KL402 FAMILY FIGURE 20-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx COE VIN- – VIN+ Cx Off (Read as ‘0’) Comparator CxINC > CxINA Compare(1) CON = 1, CREF = 0, CCH<1:0> = 01 Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CXINB CXINA VIN- COE – VIN+ CXINC Cx CxOUT Pin Comparator CxIND > CxINA Compare(1) CON = 1, CREF = 0, CCH<1:0> = 10 CXIND CXINA VINVIN+ CVREF VIN- VBG/2 Cx CxOUT Pin VIN+ CVREF Note 1: VIN- CXI
PIC24F16KL402 FAMILY REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0 CON COE CPOL CLPWR — — CEVT COUT bit 15 bit 8 R/W-0 (1) EVPOL1 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL0(1) — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator is enab
PIC24F16KL402 FAMILY REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTER (CONTINUED) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of the comparator connects to VBG/2 10 = Inverting input of the comparator connects to the CxIND pin(2) 01 = Inverting input of the comparator connects to the CxINC pin(2) 00 = Inverting input of the comparator connects to the CxINB pin Note 1: 2: If EVPOL<1:0> is set to a value other than ‘00’, the first interr
PIC24F16KL402 FAMILY 21.0 Note: COMPARATOR VOLTAGE REFERENCE 21.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 21-1). The comparator voltage reference provides a range of output voltages, with 32 distinct levels. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F16KL402 FAMILY REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparato
PIC24F16KL402 FAMILY 22.0 An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. HIGH/LOW-VOLTAGE DETECT (HLVD) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F16KL402 FAMILY REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power Ena
PIC24F16KL402 FAMILY 23.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F16KL402 FAMILY REGISTER 23-1: FBS: BOOT SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 R/C-1(1) R/C-1(1) R/C-1(1) R/C-1(1) — — — — BSS2 BSS1 BSS0 BWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-1 BSS<2:0>: Boot Segment Program Flash Code Protection bits(1) 111 = No Boot Segment; all program memory space is Gener
PIC24F16KL402 FAMILY REGISTER 23-3: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-0 R/P-0 R/P-1 IESO LPRCSEL SOSCSRC — — FNOSC2 FNOSC1 FNOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Interna
PIC24F16KL402 FAMILY REGISTER 23-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-0 R/P-0 R/P-1 FCKSM1 FCKSM0 SOSCSEL R/P-1 R/P-1 R/P-0 POSCFREQ1 POSCFREQ0 OSCIOFNC R/P-1 R/P-1 POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock
PIC24F16KL402 FAMILY REGISTER 23-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 R/P-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN1 WINDIS FWDTEN0 FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7,5 FWDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT is enabled in hardware 10 = WDT is controlled with the SWDTEN bit setting
PIC24F16KL402 FAMILY REGISTER 23-6: R/P-1 MCLRE FPOR: RESET CONFIGURATION REGISTER R/P-1 (1) BORV1 (2) R/P-1 (2) BORV0 R/P-1 I2C1SEL (3) R/P-1 U-0 R/P-1 R/P-1 PWRTEN — BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit(1) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is disabled
PIC24F16KL402 FAMILY REGISTER 23-7: FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER R/P-1 U-1 U-1 U-0 U-0 U-0 R/P-1 R/P-1 DEBUG — — — — — ICS1 ICS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled bit 6-5 Unimplemented: Read as ‘1’ bit
PIC24F16KL402 FAMILY 23.3 Unique ID A read-only Unique ID value is stored at addresses, 800802h through 800808h. This factory programmed value is unique to each microcontroller produced in the PIC24F16KL402 family. To access this region, use Table Read instructions or Program Space Visibility. REGISTER 23-8: To ensure a globally Unique ID across other Microchip microcontroller families, the “Unique ID” value should be further concatenated with the family and Device ID values stored at address, FF0000h.
PIC24F16KL402 FAMILY REGISTER 23-9: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Revi
PIC24F16KL402 FAMILY 23.4 Watchdog Timer (WDT) For the PIC24F16KL402 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit.
PIC24F16KL402 FAMILY 23.5 Program Verification and Code Protection For all devices in the PIC24F16KL402 family, code protection for the Boot Segment is controlled by the BSS<2:0> Configuration bits and the General Segment by the Configuration bit, GSS0. These bits inhibit external reads and writes to the program memory space This has no direct effect in normal execution mode. Write protection is controlled by bit, BWRP, for the Boot Segment and bit, GWRP, for the General Segment in the Configuration Word.
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 186 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 24.
PIC24F16KL402 FAMILY 24.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC24F16KL402 FAMILY 24.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24F16KL402 FAMILY 24.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC24F16KL402 FAMILY 25.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F Instruction Set Architecture (ISA) and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24F16KL402 FAMILY TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...
PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, D
PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax # of Words Description # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws,
PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None
PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR.
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 198 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 26.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24F16KL402 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F16KL402 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24F16KL402 FAMILY 26.1 DC Characteristics Voltage (VDD) FIGURE 26-1: PIC24F16KL402 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz 32 MHz Frequency Note: For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 1.8) + 8 MHz. Voltage (VDD) FIGURE 26-2: PIC24F16KL402 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz 24 MHz Frequency Note: For frequencies between 8 MHz and 24 MHz, FMAX = 13.33 MHz * (VDD – 1.
PIC24F16KL402 FAMILY TABLE 26-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 26-2: THERMAL PACKAGING CHARACTERISTICS Characteristic
PIC24F16KL402 FAMILY TABLE 26-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for Extended Param Symbol No. DC18 VHLVD TABLE 26-5: Characteristic Min Typ Max Units HLVD Voltage on VDD HLVDL<3:0> = 0000 Transition HLVDL<3:0> = 0001 — 1.85 1.94 V 1.81 1.90 2.00 V HLVDL<3:0> = 0010 1.85 1.95 2.05 V HLVDL<3:0> = 0011 1.90 2.00 2.10 V HLVDL<3:0> = 0100 1.
PIC24F16KL402 FAMILY TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)(2) Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Typical(1) Parameter No. Max Units Conditions IDD Current DC20 DC22 DC24 DC26 DC30 Note 1: 2: 0.154 0.350 1.8V mA +85V°C 0.301 0.630 3.3V — .500 1.8V mA +125°C — .800 3.3V 0.300 — 1.8V mA +85°C 0.585 — 3.3V 7.76 12.0 3.3V +85°C mA — 18.0 3.3V +125°C 1.44 — 1.
PIC24F16KL402 FAMILY TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD) DC60 Note 1: 2: 0.01 0.20 µA -40°C 0.03 0.20 µA +25°C 0.06 0.87 µA +60°C 0.20 1.35 µA +85°C — 8.00 µA +125ºC 0.01 0.54 µA -40°C 0.03 0.54 µA +25°C 0.08 1.68 µA +60°C 0.
PIC24F16KL402 FAMILY TABLE 26-9: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions 0.21 0.65 µA 1.8V 0.45 0.95 µA 3.3V — 1.30 µA 1.8V — 1.50 µA 3.3V 0.69 1.50 µA 1.8V 1.00 1.50 µA 3.3V 5.24 — µA 1.8V 5.16 11.00 µA 3.3V — 12.00 µA 1.8V — 15.00 µA 3.3V 4.15 9.00 µA 3.
PIC24F16KL402 FAMILY TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(4) DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.
PIC24F16KL402 FAMILY TABLE 26-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL DO10 OSC2/CLKO VOH DO20 Typ(1) Max Units — — 0.4 V IOL = 4.0 mA VDD = 3.6V — — 0.4 V IOL = 3.5 mA VDD = 2.0V Conditions — — 0.4 V IOL = 1.2 mA VDD = 3.6V — — 0.4 V IOL = 0.4 mA VDD = 2.0V Output High Voltage All I/O Pins DO26 Min Output Low Voltage All I/O Pins DO16 Note 1: Characteristic Standard Operating Conditions: 1.8V to 3.
PIC24F16KL402 FAMILY TABLE 26-13: DC CHARACTERISTICS: DATA EEPROM MEMORY Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Sym Min Typ(1) Max Units 100,000 — — E/W VMIN — 3.
PIC24F16KL402 FAMILY 26.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24F16KL402 Family AC characteristics and timing parameters. TABLE 26-16: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.
PIC24F16KL402 FAMILY FIGURE 26-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OS30 OS30 Q1 Q2 Q3 OSCI OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 26-18: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. OS10 Characteristic Min Typ(1) Max Units External CLKI Frequency (External clocks allowed only in EC mode) DC 4 — — 32 8 MHz MHz EC ECPLL Oscillator Frequency 0.
PIC24F16KL402 FAMILY TABLE 26-19: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24F16KL402 FAMILY FIGURE 26-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value New Value DO31 DO32 Note: Refer to Figure 26-3 for load conditions. TABLE 26-22: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 1.8V to 3.
PIC24F16KL402 FAMILY TABLE 26-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max.
PIC24F16KL402 FAMILY FIGURE 26-6: CAPTURE/COMPARE/PWM TIMINGS (ECCP1, ECCP2 MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 26-3 for load conditions. TABLE 26-26: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP1, ECCP2 MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No Prescaler Time With Prescaler 0.5 TCY + 20 — ns 20 — ns CCPx Input High Time 0.
PIC24F16KL402 FAMILY FIGURE 26-7: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCKx (CKP = 0) 78 79 79 78 SCKx (CKP = 1) MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 26-3 for load conditions. TABLE 26-27: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC24F16KL402 FAMILY FIGURE 26-8: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCKx (CKP = 0) 79 73 SCKx (CKP = 1) 78 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDIx bit 6 - - - - 1 MSb In LSb In 74 Note: Refer to Figure 26-3 for load conditions. TABLE 26-28: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC24F16KL402 FAMILY FIGURE 26-9: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 83 71 72 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In 77 bit 6 - - - - 1 LSb In 74 73 Refer to Figure 26-3 for load conditions. Note: TABLE 26-29: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC24F16KL402 FAMILY FIGURE 26-10: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKP = 0) 70 83 71 72 73 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 77 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure 26-3 for load conditions. TABLE 26-30: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC24F16KL402 FAMILY FIGURE 26-11: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Condition Note: Stop Condition Refer to Figure 26-3 for load conditions. TABLE 26-31: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC24F16KL402 FAMILY TABLE 26-32: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR Characteristic Clock High Time Min Max Units 100 kHz mode 4.0 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz MSSP module 1.5 — TCY 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz MSSP module 1.
PIC24F16KL402 FAMILY FIGURE 26-13: MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Condition Note: Stop Condition Refer to Figure 26-3 for load conditions. TABLE 26-33: I2C™ BUS START/STOP BITS REQUIREMENTS (MASTER MODE) Param. Symbol No.
PIC24F16KL402 FAMILY MSSPx I2C™ BUS DATA TIMING FIGURE 26-14: 103 102 100 101 SCLx 90 106 91 SDAx In 109 92 107 110 109 SDAx Out Note: Refer to Figure 26-3 for load conditions. TABLE 26-34: I2C™ BUS DATA REQUIREMENTS (MASTER MODE) Param. Symbol No.
PIC24F16KL402 FAMILY TABLE 26-35: A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. Symbol Characteristic Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of: VDD – 0.3 or 1.8 — Lesser of: VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.
PIC24F16KL402 FAMILY TABLE 26-36: A/D CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
PIC24F16KL402 FAMILY 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 14-Lead PDIP (300 mil) Example PIC24F04KL100 -I/P e3 1316012 20-Lead PDIP (300 mil) Example PIC24F08KL201 -I/P e3 1316012 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SPDIP (.300”) Example PIC24F16KL302 -I/SP e3 1316012 Legend: XX...
PIC24F16KL402 FAMILY 20-Lead SOIC (7.50 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC24F08KL301 -I/SO e3 1316012 YYWWNNN 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4 mm) XXXXXXXX YYWW NNN 20-Lead SSOP (5.30 mm) Example PIC24F08KL302 -I/SO e3 1316012 Example 24F08KL1 1316 012 Example PIC24F08KL 401-I/SS e3 1316012 DS30001037C-page 226 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 28-Lead SSOP (5.30 mm) Example PIC24F08KL 402-I/SS e3 1316012 20-Lead QFN (5x5x0.9 mm) PIN 1 Example PIN 1 28-Lead QFN (5x5x0.9 mm) PIN 1 24F08 KL301 -I/MQ e3 1316012 Example PIN 1 24F08 KL302 -I/MQ e3 1316012 28-Lead QFN (6x6 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 27.2 Package Details The following sections give the technical details of the packages.
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PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 232 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 234 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 236 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 238 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
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PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
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PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-120A DS30001037C-page 244 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 246 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern With 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-2140A DS30001037C-page 248 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY !" * + , $ - .
PIC24F16KL402 FAMILY !" * + , $ - . /0/ *+ 1 % )(( 2 - % 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 DS30001037C-page 250 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (September 2011) Original data sheet for the PIC24F16KL402 family of devices. Revision B (November 2011) Updates DC Specifications in Tables 26-6 through 26-9 (all Typical and Maximum values). Updates AC Specifications in Tables 26-7 through 26-30 (SPI Timing Requirements) with the addition of the FSCK specification. Other minor typographic corrections throughout.
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 252 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY INDEX A C A/D C Compilers MPLAB XC Compilers .............................................. 188 Capture/Compare/PWM (CCP) ........................................ 125 CCP/ECCP CCP I/O Pins ............................................................ 125 Timer Selection......................................................... 125 Code Examples Data EEPROM Bulk Erase ......................................... 57 Data EEPROM Unlock Sequence ..............................
PIC24F16KL402 FAMILY DC Characteristics BOR Trip Points ........................................................ 202 Comparator ............................................................... 208 Comparator Voltage Reference ................................ 208 Data EEPROM Memory ............................................ 208 High/Low-Voltage Detect .......................................... 202 I/O Pin Input Specifications ....................................... 206 I/O Pin Output Specifications ........
PIC24F16KL402 FAMILY Program Memory Address Space............................................................ 31 Data EEPROM............................................................ 32 Device Configuration Words ....................................... 32 Hard Memory Vectors ................................................. 32 Organization................................................................ 32 Program Space Memory Map ...............................................................
PIC24F16KL402 FAMILY T U Timer1 ............................................................................... 115 Timer2 ............................................................................... 117 Timer3 ............................................................................... 119 Oscillator ................................................................... 119 Overflow Interrupt ..................................................... 119 Timer4 .............................................
PIC24F16KL402 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 258 2011-2013 Microchip Technology Inc.
PIC24F16KL402 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC24F16KL402 FAMILY NOTES: DS30001037C-page 260 2011-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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