Datasheet

PIC24F04KA201 FAMILY
DS39937B-page 54 Preliminary © 2009 Microchip Technology Inc.
6.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 6-3. Note that the system Reset
signal, SYSRST
, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST
delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST
signal is released.
TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type Clock Source SYSRST Delay
System Clock
Delay
Notes
POR
(6)
EC TPOR + TPWRT — 1, 2
FRC, FRCDIV TPOR + TPWRT TFRC 1, 2, 3
LPRC T
POR + TPWRT TLPRC 1, 2, 3
ECPLL TPOR + TPWRT TLOCK 1, 2, 4
FRCPLL TPOR + TPWRT TFRC + TLOCK 1, 2, 3, 4
XT, HS, SOSC T
POR+ TPWRT TOST 1, 2, 5
XTPLL, HSPLL TPOR + TPWRT TOST + TLOCK 1, 2, 4, 5
BOR EC TPWRT — 2
FRC, FRCDIV T
PWRT TFRC 2, 3
LPRC TPWRT TLPRC 2, 3
ECPLL TPWRT TLOCK 2, 4
FRCPLL T
PWRT TFRC + TLOCK 2, 3, 4
XT, HS, SOSC TPWRT TOST 2, 5
XTPLL, HSPLL TPWRT TFRC + TLOCK 2, 3, 4
All Others Any Clock — — None
Note 1: T
POR = Power-on Reset delay.
2: TPWRT = 64 ms nominal if the Power-up Timer is enabled; otherwise, it is zero.
3: T
FRC and TLPRC = RC Oscillator start-up times.
4: T
LOCK = PLL lock time.
5: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing
oscillator clock to the system.
6: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC,
and in such cases, FRC start-up time is valid.
Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.