Datasheet

PIC24F04KA201 FAMILY

TABLE 6-1: RESET FLAG BIT OPERATION

6.1 Clock Source Selection at Reset

If clock switching is enabled, the system clock source at

device Reset is chosen as shown in Table 6-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator Configuration bits.

Refer to Section 8.0 “Oscillator Configuration” for

further details.

TABLE 6-2: OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

bit 0 POR: Power-on Reset Flag bit

1 = A Power-up Reset has occurred

0 = A Power-up Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

Flag Bit Setting Event Clearing Event

TRAPR (RCON<15>) Trap Conflict Event POR

IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR

CM (RCON<9>) Configuration Mismatch Reset POR

EXTR (RCON<7>) MCLR

Reset POR

SWR (RCON<6>) RESET Instruction POR

WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR

SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR

IDLE (RCON<2>) PWRSAV #IDLE Instruction POR

BOR (RCON<1>) POR, BOR —

POR (RCON<0>) POR —

DPSLP (RCON<10>) PWRSAV #SLEEP instruction with DSCON <DSEN> set POR

Note: All Reset flag bits may be set or cleared by the user software.

(1)

(CONTINUED)

Reset Type Clock Source Determinant

POR FNOSC Configuration bits

(FNOSC<10:8>)

BOR

MCLR

COSC Control bits

(OSCCON<14:12>)

WDTO

SWR