Datasheet

PIC24F04KA201 FAMILY
DS39937B-page 150 Preliminary © 2009 Microchip Technology Inc.
EQUATION 19-1: A/D CONVERSION CLOCK PERIOD
(1)
FIGURE 19-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.
TAD = TCY • (ADCS + 1)
TAD
TCY
ADCS = – 1
CPIN
VA
Rs
ANx
V
T = 0.6V
V
T = 0.6V
I
LEAKAGE
RIC ≤ 250W
Sampling
Switch
R
SS
CHOLD
= DAC capacitance
V
SS
VDD
= 4.4 pF (Typical)
±500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
RSS ≤ 5 kΩ (Typical)
6-11 pF
(Typical)