Datasheet

PIC24F04KA201 FAMILY

bit 5 ACKDT: Acknowledge Data bit (when operating as I

C master; applicable during master receive)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1 = Sends NACK during Acknowledge

0 = Sends ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit

(when operating as I

C master; applicable during master receive)

1 = Initiates Acknowledge sequence on SDA1 and SCL1 pins and transmits ACKDT data bit; hardware

clear at end of master Acknowledge sequence

0 = Acknowledge sequence not in progress

bit 3 RCEN: Receive Enable bit (when operating as I

C master)

1 = Enables Receive mode for I

C; hardware clear at end of eighth bit of master receive data byte

0 = Receive sequence not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as I

C master)

1 = Initiates Stop condition on SDA1 and SCL1 pins; hardware clear at end of master Stop sequence

0 = Stop condition not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I

C master)

1 = Initiates Repeated Start condition on SDA1 and SCL1 pins; hardware clear at end of master

Repeated Start sequence

0 = Repeated Start condition not in progress

bit 0 SEN: Start Condition Enable bit (when operating as I

C master)

1 = Initiates Start condition on SDA1 and SCL1 pins; hardware clear at end of master Start sequence

0 = Start condition not in progress