PIC24F04KA201 Family Data Sheet 14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP™ Technology © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC24F04KA201 FAMILY 14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP™ Technology Power Management Modes: Analog Features: • • • • • 10-Bit, up to 9-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU): - Used for capacitance sensing - Compatible with mTouch™ capacitive sensing - Time measurement, down to 1 ns resol
PIC24F04KA201 FAMILY Pin Diagrams 14-Pin PDIP, TSSOP(1) 1 2 3 4 5 6 7 PIC24F04KA200 MCLR/VPP/RA5 PGC2/AN0/VREF+/CN2/RA0 PGD2/AN1/VREF-/CN3/RA1 OSCI/CLKI/AN4/C1INB/CN30/RA2 OSCO/CLKO/AN5/C1INA/CN29/RA3 PGD3/SOSCI/AN2/C2INB/HLVDIN/CN1/RB4 PGC3/SOSCO/AN3/C2INA/T1CK/CN0/RA4 14 13 12 11 10 9 8 VDD VSS REFO/U1RX/SS1/T2CK/T3CK/INT0/CTPLS/CN11/RB15 AN10/CVREF/U1TX/SDI1/OCFA/C1OUT/INT1/CTED2/CN12/RB14 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 SDA1/U1BCLK/U1RTS/SDO1/CN21/RB9 SCL1/U1CTS/SCK1/CN22/RB8 20-Pin PDIP, SSOP, SO
PIC24F04KA201 FAMILY Pin Diagrams (Continued) PGD2/AN1/VREF-/CN3/RA1 PGC2/AN0/VREF+/CN2/RA0 MCLR/VPP/RA5 VDD VSS 20-Pin QFN(1,2) 20 19 18 17 16 AN2/C2INB/CN4/RB0 AN3/C2INA/CN5/RB1 15 1 14 2 U1RX/U1BCLK/CN6/RB2 3 PIC24F04KA201 13 OSCI/CLKI/AN4/C1INB/CN30/RA2 4 12 OSCO/CLKO/AN5/C1INA/CN29/RA3 5 11 REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 PGD3/SOSCI/CN1/RB4 PGC3/SOSCO/T1CK/CN0/RA4 U1T
PIC24F04KA201 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 15 3.0 CPU ....................................................................................................
PIC24F04KA201 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC24F04KA201 FAMILY NOTES: DS39937B-page 6 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 1.0 1.1.2 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24F04KA200 • PIC24F04KA201 The PIC24F04KA201 family introduces a new line of extreme low-power Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance.
PIC24F04KA201 FAMILY The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.3 1.1.4 1.
PIC24F04KA201 FAMILY Features Operating Frequency PIC24F04KA201 DEVICE FEATURES FOR THE PIC24F04KA201 FAMILY PIC24F04KA200 TABLE 1-1: DC – 32 MHz Program Memory (bytes) 4K Program Memory (instructions) 1408 Data Memory (bytes) 512 Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins 25 (21/4) PORTA<6:0> PORTB<15:14, 9:8, 4> PORTA<6:0> PORTB<15:12, 9:7, 4, 2:0> 12 18 Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) 3 1 Input Capture Channels 1 Output Compa
PIC24F04KA201 FAMILY FIGURE 1-1: PIC24F04KA201 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller 16 16 16 8 Data Latch PSV and Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTA(1) RA<6:0> 16 23 16 Read AGU Write AGU Address Latch Program Memory PORTB(1) RB<15:12, 9:7> RB<4, 2:0> Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 Inst Register Instruction Decode and Control Control
PIC24F04KA201 FAMILY TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS Pin Number 14-Pin PDIP/TSSOP/ SOIC 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN I/O Input Buffer AN0 2 2 19 I ANA AN1 3 3 20 I ANA AN2 6 4 1 I ANA AN3 7 5 2 I ANA AN4 4 7 4 I ANA AN5 5 8 5 I ANA AN10 11 17 14 I ANA AN11 — 16 13 I ANA AN12 — 15 12 I ANA U1BCLK 9 13 10 O — C1INA 5 8 5 I ANA Comparator 1 Input A (Positive input) C1INB 4 7 4 I ANA Comparator 1 Input B (Ne
PIC24F04KA201 FAMILY TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 14-Pin PDIP/TSSOP/ SOIC 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN I/O Input Buffer 6 15 12 I ANA HLVDIN Description HLVD Voltage Input MCLR 1 1 18 I ST OC1 10 14 11 O — Output Compare/PWM Outputs OCFA 11 17 14 I — Output Compare Fault A OSCI 4 7 4 I ANA Main Oscillator Input Connection OSCO 5 8 5 O ANA Main Oscillator Output Connection PGC2 2 2 19 I/O ST In
PIC24F04KA201 FAMILY TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 14-Pin PDIP/TSSOP/ SOIC 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN I/O Input Buffer VDD 14 20 17 P — Positive Supply for Peripheral Digital Logic and I/O Pins Programming Mode Entry Voltage Function Description VPP 1 1 18 P — VREF- 3 3 20 I ANA A/D and Comparator Reference Voltage (low) Input VREF+ 2 2 19 I ANA A/D and Comparator Reference Voltage (high) Input 13 19 16 P — VSS Lege
PIC24F04KA201 FAMILY NOTES: DS39937B-page 14 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) VDD R1 R2 VCAP/VDDCORE C1 These pins must also be connected if they are being used in the end application: • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.
PIC24F04KA201 FAMILY 2.2 2.2.1 Power Supply Pins 2.3 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24F04KA201 FAMILY 2.4 Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) Note: 2.5 This section applies only to PIC24F devices with an on-chip voltage regulator. The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground.
PIC24F04KA201 FAMILY 2.6 External Oscillator Pins 2.7 Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24F04KA201 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the CPU, refer to the “PIC24F Family Reference Manual”, Section 2. “CPU” (DS39703). The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field.
PIC24F04KA201 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory Data Latch EA MUX Address Bus ROM Latch 24 16 Instruction Decode and Control Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support Literal Data 16 16 x 16 W Regist
PIC24F04KA201 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL — — — — — — — DC IPL RA N OV Z C 2 1 0 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register
PIC24F04KA201 FAMILY 3.
PIC24F04KA201 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(1) PSV — — bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)
PIC24F04KA201 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1.
PIC24F04KA201 FAMILY 4.0 MEMORY ORGANIZATION FIGURE 4-1: As with Harvard architecture devices, the PIC24F microcontrollers feature separate program and data memory space and busing. This architecture also allows the direct access of program memory from the data space during code execution. 4.
PIC24F04KA201 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION device interrupt sources to be handled by separate ISRs. Section 7.1 “Interrupt Vector (IVT) Table” discusses the interrupt vector tables more in detail. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented.
PIC24F04KA201 FAMILY 4.2 4.2.1 Data Address Space DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all the data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range.
PIC24F04KA201 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory.
© 2009 Microchip Technology Inc.
ICN REGISTER MAP File Addr Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CNEN1 0060 — CN14IE(1) CN13IE(1) CN12IE CN11IE — — CN8IE — CN6IE(1) CN5IE(1) CN4IE(1) CN3IE CN2IE CN1IE CN0IE 0000 CN22IE CN21IE — — — — — 0000 CNEN2 0062 — CNPU1 0068 — CNPU2 006A — CNPD1 0070 — CNPD2 0072 CN30IE CN29IE — — CN14PUE(1) CN13PUE(1) CN12PUE CN11PUE CN30PUE CN29PUE — — CN14PDE(1) CN13PDE(1) CN12PDE CN11
© 2009 Microchip Technology Inc.
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF I2C1BRG 0204 — — — — — — — I2C1CON 0206 I2CEN — A10M DISSLW SMEN GCEN STREN I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV I2C1ADD 020A — — — — — — I2C1MSK 020C — — — — — — Legend: Addr Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2C1 Baud Rate G
© 2009 Microchip Technology Inc.
File Name Addr ADC REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Preliminary ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC Data Buffer 7 xxxx ADC1BUF
© 2009 Microchip Technology Inc.
NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets NVMCON 0760 WR WREN WRERR PGMONLY — — — — — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) NVMKEY 0766 — — — — — — — — NVMKEY7 NVMKEY6 Legend: Note 1: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only.
PIC24F04KA201 FAMILY 4.2.5 SOFTWARE STACK 4.3 In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as depicted in Figure 4-4. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.
PIC24F04KA201 FAMILY TABLE 4-22: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 2: 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0>(2) Data EA<14:0
PIC24F04KA201 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by 2 for each successive 24-bit program word.
PIC24F04KA201 FAMILY FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space Data EA<15:0> TBLPAG 23 00 23 15 16 8 0 00000000 0 000000h 00000000 00000000 00000000 002BFEh ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W 800000h 4.3.
PIC24F04KA201 FAMILY Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space PSVPAG 23 00 15 Data Space 0 000000h 0000h Data EA<14:0> 002BFEh The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... 8000h PSV Area ...
PIC24F04KA201 FAMILY NOTES: DS39937B-page 42 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Flash programming, refer to the “PIC24F Family Reference Manual”, Section 4. “Program Memory” (DS39715). The PIC24F04KA201 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with VDD over 1.
PIC24F04KA201 FAMILY 5.2 RTSP Operation 5.3 The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time and to program one row at a time. It is also possible to program single words. The 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks and single row write block (96 bytes) are edge-aligned, from the beginning of program memory.
PIC24F04KA201 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 U-0 — bit 8 R/W-0 ERASE R/W-0 NVMOP5 R/W-0 (1) R/W-0 (1) R/W-0 (1) NVMOP4 NVMOP3 NVMOP2 R/W-0 (1) NVMOP1 R/W-0 (1) NVMOP0(1) bit 7 bit 0 SO = Settable Only bit Legend: HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, read a
PIC24F04KA201 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is: 1. 2. 3. Read a row of program memory (32 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase a row (see Example 5-1): a) Set the NVMOP bits (NVMCON<5:0>) to ‘011000’ to configure for row erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits.
PIC24F04KA201 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE // C example using MPLAB C30 int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Variable located in Pgm Memory unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); offset = &progAddr & 0xFFFF; // Initialize PM Page Boundary SFR // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dumm
PIC24F04KA201 FAMILY EXAMPLE 5-3: LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row programming operations MOV #0x4004, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,
PIC24F04KA201 FAMILY EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE DISI #5 MOV MOV MOV MOV BSET NOP NOP BTSC BRA #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR EXAMPLE 5-6: ; Block all interrupts for next 5 instructions NVMCON, #15 $-2 ; ; ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence 2 NOPs required after setting WR Wait for the sequence to be completed INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE // C example using MPLAB C30 as
PIC24F04KA201 FAMILY NOTES: DS39937B-page 50 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 6.0 RESETS Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Resets, refer to the “PIC24F Family Reference Manual”, Section 40. “Reset with Programmable Brown-out Reset” (DS39728). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24F04KA201 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0, HS TRAPR bit 15 R/W-0, HS IOPUWR R/W-0 SBOREN U-0 — U-0 — R/C-0, HS DPSLP U-0 — R/W-0, HS EXTR bit 7 R/W-0, HS SWR R/W-0, HS SWDTEN(2) R/W-0, HS WDTO R/W-0, HS SLEEP R/W-0, HS IDLE R/W-1, HS BOR Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 C = Clearable bit W = Writable bit ‘1’ = Bit is set R/W-0 PMSLP bit 8 R/W-1, HS
PIC24F04KA201 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 6-1: bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred Note 1: 2: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
PIC24F04KA201 FAMILY 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released.
PIC24F04KA201 FAMILY 6.3 6.3.2 Brown-out Reset (BOR) The PIC24F04KA201 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the and (BOREN<1:0>) Configuration bits (FPOR<6:5,1:0>). There are a total of four BOR configurations, which are provided in Table 6.3.1. The BOR threshold is set by the BORV<1:0> bits.
PIC24F04KA201 FAMILY 6.3.5 POR AND LONG OSCILLATOR START-UP TIMES 6.4 The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24F04KA201 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Interrupt Controller, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU.
PIC24F04KA201 FAMILY TABLE 7-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h Reserved 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations AIVT Address Flag Enable 00002Eh 00012Eh IFS0<13> IEC0<13> IP
PIC24F04KA201 FAMILY 7.3 Interrupt Control and Status Registers The PIC24F04KA201 family of devices implements a total of 23 registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0, IFS1, IFS3 and IFS4 IEC0, IEC1, IEC3 and IEC4 IPC0 through IPC5, IPC7 and IPC15 through IPC19 • INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources.
PIC24F04KA201 FAMILY REGISTER 7-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — DC(1) bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 U
PIC24F04KA201 FAMILY REGISTER 7-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 R/C-0, HSC (2) — IPL3 R/W-0 U-0 U-0 — — (1) PSV bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Pri
PIC24F04KA201 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrup
PIC24F04KA201 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Us
PIC24F04KA201 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0, HS NVMIF bit 15 U-0 — R/W-0, HS AD1IF R/W-0, HS U1TXIF R/W-0, HS U1RXIF R/W-0, HS SPI1IF R/W-0, HS SPF1IF R/W-0, HS T3IF bit 8 R/W-0, HS T2IF bit 7 U-0 — U-0 — U-0 — R/W-0, HS T1IF R/W-0, HS OC1IF R/W-0, HS IC1IF R/W-0, HS INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-4 bit 3 bit 2 bit 1 bit 0 HS = Hardware Settable bit W =
PIC24F04KA201 FAMILY REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 — bit 15 U-0 — U-0 — U-0 — R/W-0, HS INT2IF U-0 — U-0 — Legend: R = Readable bit -n = Value at POR bit 12-5 bit 4 bit 3 bit 2 bit 1 bit 0 U-0 — U-0 — bit 8 U-0 — R/W-0, HS INT1IF R/W-0, HS CNIF bit 7 bit 15-14 bit 13 U-0 — R/W-0, HS CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 HS = Hardware Settable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC24F04KA201 FAMILY REGISTER 7-7: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS — — CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS U-0 — — — — — — U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Sta
PIC24F04KA201 FAMILY REGISTER 7-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 NVMIE bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 U-0 — U-0 — U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ =
PIC24F04KA201 FAMILY REGISTER 7-9: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 — bit 15 U-0 — U-0 — U-0 — R/W-0 INT2IE U-0 — U-0 — Legend: R = Readable bit -n = Value at POR bit 12-5 bit 4 bit 3 bit 2 bit 1 bit 0 U-0 — U-0 — bit 8 U-0 — R/W-0 INT1IE R/W-0 CNIE bit 7 bit 15-14 bit 13 U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ INT2IE: Ext
PIC24F04KA201 FAMILY REGISTER 7-10: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request enabled 0 =
PIC24F04KA201 FAMILY REGISTER 7-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1I
PIC24F04KA201 FAMILY REGISTER 7-12: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T2IP2 T2IP1 T2IP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority
PIC24F04KA201 FAMILY REGISTER 7-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-1
PIC24F04KA201 FAMILY REGISTER 7-14: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP<2:0>: NVM Inter
PIC24F04KA201 FAMILY REGISTER 7-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNI
PIC24F04KA201 FAMILY REGISTER 7-16: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt
PIC24F04KA201 FAMILY REGISTER 7-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT2IP2 INT2IP1 INT2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt
PIC24F04KA201 FAMILY REGISTER 7-18: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interr
PIC24F04KA201 FAMILY REGISTER 7-19: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits
PIC24F04KA201 FAMILY REGISTER 7-21: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 CPUIRQ — VHOLD — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but
PIC24F04KA201 FAMILY 7.4 7.4.3 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24F04KA201 FAMILY 8.0 • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC mode. When using an external clock source, the current consumption is reduced by setting the declaration bits to the expected frequency range. • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown.
PIC24F04KA201 FAMILY 8.1 CPU Clocking Scheme 8.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24F04KA201 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC<5>) bit.
PIC24F04KA201 FAMILY 8.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers (SFRs): • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 8-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 8-1: The Clock Divider register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator.
PIC24F04KA201 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24F04KA201 FAMILY REGISTER 8-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and
PIC24F04KA201 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tu
PIC24F04KA201 FAMILY 8.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 8.4.1 The primary oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits.
PIC24F04KA201 FAMILY The following code sequence for a clock switch is recommended: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence.
PIC24F04KA201 FAMILY REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference
PIC24F04KA201 FAMILY NOTES: DS39937B-page 90 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 9.0 Note: The assembly syntax of the PWRSAV instruction is shown in Example 9-1. POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 39. “Power-Saving Features with Deep Sleep” (DS39727).
PIC24F04KA201 FAMILY 9.2.2 IDLE MODE 9.2.4.1 Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24F04KA201 FAMILY Note: Any interrupt pending when entering Deep Sleep mode is cleared, Exiting Deep Sleep mode generally does not retain the state of the device and is equivalent to a Power-on Reset (POR) of the device. Exceptions to this include the DSGPRx registers and DSWSRC. Wake-up events that occur from the time Deep Sleep exits until the time the POR sequence completes are ignored, and are not be captured in the DSWAKE register. The sequence for exiting Deep Sleep mode is: 1. 2. 3. 4. 5. 6.
PIC24F04KA201 FAMILY 9.2.4.5 Deep Sleep WDT 9.2.4.8 To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS<7>). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (FDS<4>). The postscaler options are programmed by the DSWDTPS<3:0> Configuration bits (FDS<3:0>). The minimum time-out period that can be achieved is 2.
PIC24F04KA201 FAMILY DSCON: DEEP SLEEP CONTROL REGISTER(1) REGISTER 9-1: R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DSEN — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — U-0 — U-0 — R/W-0 (2) DSBOR R/C-0, HS RELEASE bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DSEN: Deep Sleep Enable bit 1 = Enters Deep
PIC24F04KA201 FAMILY DSWSRC: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) REGISTER 9-2: U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS U-0 R/W-0, HS U-0 R/W-0, HS DSFLT — — DSWDT — DSMCLR — DSPOR(2,3) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Rea
PIC24F04KA201 FAMILY 9.2.5 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode is completed. The device will then wake-up from Sleep or Idle mode. 9.3 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical.
PIC24F04KA201 FAMILY NOTES: DS39937B-page 98 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 10.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the I/O Ports, refer to the “PIC24F Family Reference Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24F04KA201 family devices do not support Peripheral Pin Select features.
PIC24F04KA201 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 10.
PIC24F04KA201 FAMILY 11.0 Note: Figure 11-1 presents a block diagram of the 16-bit Timer1 module. TIMER1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3. 4. The Timer1 module is a 16-bit timer which can operate as a free-running, interval timer/counter.
PIC24F04KA201 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as
PIC24F04KA201 FAMILY 12.0 Note: To configure Timer2/3 for 32-bit operation: TIMER2/3 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The Timer2/3 module is a 32-bit timer, which can also be configured as two independent 16-bit timers with selectable operating modes.
PIC24F04KA201 FAMILY FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE TGATE TCS Q 1 Set T3IF Q 0 PR3 ADC Event Trigger Equal D CK PR2 Comparator MSB LSB TMR3 Reset TMR2 Sync 16 Read TMR2 (1) Write TMR2(1) 16 TMR3HLD 16 16 Data Bus<15:0> Note 1: DS39937B-page 104 The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register.
PIC24F04KA201 FAMILY FIGURE 12-2: TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON T2CK TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS TCY 1 Set T2IF 0 Reset Equal Q D Q CK TGATE TMR2 Sync Comparator PR2 FIGURE 12-3: TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON Sync T3CK TCKPS<1:0> 2 1x Prescaler 1, 8, 64, 256 01 00 TGATE TCY 1 Set T3IF 0 Reset ADC Event Trigger Equal Q D Q CK TCS TGATE TMR3 Comparator PR3 © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer2 On bit When T2CON<3> = 1: 1 = Starts 32-bit Timer2/3 0 = Stops 32-bit Timer2/3 When T2
PIC24F04KA201 FAMILY REGISTER 12-2: T3CON: TIMER3 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer3 On bit(1) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimple
PIC24F04KA201 FAMILY NOTES: DS39937B-page 108 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 13.0 INPUT CAPTURE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Input Capture, refer to the “PIC24F Family Reference Manual”, Section 15. “Input Capture” (DS39701). The input capture module is used to capture a timer value from one of two selectable time bases upon an event on an input pin.
PIC24F04KA201 FAMILY 13.
PIC24F04KA201 FAMILY 14.0 Note: 14.1 OUTPUT COMPARE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Output Compare, refer to the “PIC24F Family Reference Manual”, Section 16. “Output Compare” (DS39706).
PIC24F04KA201 FAMILY 14.3 EQUATION 14-1: Pulse-Width Modulation (PWM) Mode PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] The following steps should be taken when configuring the output compare module for PWM operation: 1. 2. 3. 4. 5. 6. Set the PWM period by writing to the selected Timer Period register (PRy). Set the PWM duty cycle by writing to the OC1RS register. Write the OC1R register with the initial duty cycle.
PIC24F04KA201 FAMILY EXAMPLE 14-1: 1. PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 μs PWM Period = (PR2 + 1) • TCY • (Timer 2 Prescale Value) 19.2 μs = (PR2 + 1) • 62.5 ns • 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.
PIC24F04KA201 FAMILY FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OC1IF(1) OC1RS(1) Output Logic OC1R(1) 3 OCM<2:0> Mode Select Comparator 0 16 OCTSEL 1 OC1(1) Output Enable OCFA(2) 1 16 TMR Register Inputs from Time Bases(3) Note 1: 2: 3: 0 S Q R Period Match Signals from Time Bases(3) Where ‘x’ is depicted, reference is made to the registers associated with the respective Output Compare Channel 1. OCFA pin controls OC1 channel.
PIC24F04KA201 FAMILY 14.
PIC24F04KA201 FAMILY REGISTER 14-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — R/W-0 SMBUSDEL R/W-0 (2) OC1TRIS (1) U-0 U-0 R/W-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 3 OC1TRIS: OC1 Output Tri-State Select bit(1)
PIC24F04KA201 FAMILY 15.0 Note: The devices of the PIC24F04KA201 family offer one SPI module on a device. SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Serial Peripheral Interface, refer to the “PIC24F Family Reference Manual”, Section 23. “Serial Peripheral Interface (SPI)” (DS39699).
PIC24F04KA201 FAMILY FIGURE 15-1: SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE) SCK1 1:1 to 1:8 Secondary Prescaler SS1/FSYNC1 Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPI1CON1<1:0> SPI1CON1<4:2> Shift Control SDO1 Enable Master Clock bit 0 SDI1 FCY SPI1SR Transfer Transfer SPI1BUF Read SPI1BUF Write SPI1BUF 16 Internal Data Bus DS39937B-page 118 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY To set up the SPI module for the Enhanced Buffer Master (EBM) mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register. b) Set the respective SPI1IE bit in the IEC0 register. c) Write the respective SPI1IPx bits in the IPC2 register. Write the desired settings to the SPI1CON1 and SPI1CON2 registers with the MSTEN bit (SPI1CON1<5>) = 1.
PIC24F04KA201 FAMILY REGISTER 15-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER R/W-0 SPIEN bit 15 U-0 — R/W-0 SPISIDL U-0 — U-0 — R-0, HSC SPIBEC2 R-0, HSC SPIBEC1 R-0, HSC SPIBEC0 bit 8 R-0,HSC SRMPT bit 7 R/C-0, HS SPIROV R/W-0, HSC SRXMPT R/W-0 SISEL2 R/W-0 SISEL1 R/W-0 SISEL0 R-0, HSC SPITBF R-0, HSC SPIRBF bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at P
PIC24F04KA201 FAMILY REGISTER 15-1: bit 1 bit 0 SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED) SPITBF: SPI1 Transmit Buffer Full Status bit 1 = Transmit not yet started, SPI1TXB is full 0 = Transmit started, SPI1TXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPI1BUF location, loading SPI1TXB. Automatically cleared in hardware when SPI1 module transfers data from SPI1TXB to SPI1SR.
PIC24F04KA201 FAMILY REGISTER 15-2: SPI1CON1: SPI1 CONTROL REGISTER 1 U-0 — bit 15 U-0 — U-0 — R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 SSEN bit 7 R/W-0 CKP R/W-0 MSTEN R/W-0 SPRE2 R/W-0 SPRE1 R/W-0 SPRE0 R/W-0 PPRE1 R/W-0 PPRE0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = B
PIC24F04KA201 FAMILY REGISTER 15-2: bit 1-0 Note 1: SPI1CON1: SPI1 CONTROL REGISTER 1 (CONTINUED) PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).
PIC24F04KA201 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FCY FSCK = Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
PIC24F04KA201 FAMILY 16.0 Note: INTER-INTEGRATED CIRCUIT (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Inter-Integrated Circuit, refer to the “PIC24F Family Reference Manual”, Section 24. “Inter-Integrated Circuit (I2C™)” (DS39702). 16.2 The details of sending a message in Master mode depends on the communications protocol for the device being communicated with.
PIC24F04KA201 FAMILY FIGURE 16-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2C1RCV SCL1 Read Shift Clock I2C1RSR LSB SDA1 Address Match Match Detect Write I2C1MSK Write Read I2C1ADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2C1STAT Collision Detect Read Write I2C1CON Acknowledge Generation Read Clock Stretching Write I2C1TRN LSB Read Shift Clock Reload Control Write BRG Down Counter I2C1BRG Read TCY/2 DS39937B-page 126 Preliminary © 2009 Micro
PIC24F04KA201 FAMILY 16.3 Setting Baud Rate When Operating as a Bus Master 16.4 The I2C1MSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2C1MSK register causes the slave module to respond whether the corresponding address bit value is ‘0’ or ‘1’. For example, when I2C1MSK is set to ‘00100000’, the slave module will detect both addresses: ‘0000000’ and ‘00100000’.
PIC24F04KA201 FAMILY REGISTER 16-1: I2C1CON: I2C1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit
PIC24F04KA201 FAMILY REGISTER 16-1: I2C1CON: I2C1 CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
PIC24F04KA201 FAMILY REGISTER 16-2: I2C1STAT: I2C1 STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS IWCOL I2COV R-0, HSC R/C-0, HSC R/C-0, HSC D/A P R-0, HSC R-0, HSC R-0, HSC R/W RBF TBF S bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at
PIC24F04KA201 FAMILY REGISTER 16-2: I2C1STAT: I2C1 STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
PIC24F04KA201 FAMILY REGISTER 16-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMS
PIC24F04KA201 FAMILY 17.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Universal Asynchronous Receiver Transmitter, refer to the “PIC24F Family Reference Manual”, Section 21. “UART” (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in this PIC24F device family.
PIC24F04KA201 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The U1BRG register controls the period of a free-running, 16-bit timer. Equation 17-1 provides the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: Baud Rate = The maximum baud rate (BRGH = 0) possible is FCY/16 (for U1BRG = 0) and the minimum baud rate possible is FCY/(16 * 65536).
PIC24F04KA201 FAMILY 17.2 1. 2. 3. 4. 5. 6. 2. 3. 4. 5. 6. 17.5 Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the U1BRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to lower byte of U1TXREG word.
PIC24F04KA201 FAMILY REGISTER 17-1: U1MODE: UART1 MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2) R/W-0(2) UARTEN — USIDL IREN(1) RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x
PIC24F04KA201 FAMILY REGISTER 17-1: U1MODE: UART1 MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1:
PIC24F04KA201 FAMILY REGISTER 17-2: U1STA: UART1 STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writ
PIC24F04KA201 FAMILY REGISTER 17-2: U1STA: UART1 STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
PIC24F04KA201 FAMILY REGISTER 17-3: U1TXREG: UART1 TRANSMIT REGISTER U-x — bit 15 U-x — U-x — U-x — U-x — U-x — U-x — W-x UTX8 bit 8 W-x UTX7 bit 7 W-x UTX6 W-x UTX5 W-x UTX4 W-x UTX3 W-x UTX2 W-x UTX1 W-x UTX0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 bit 7-0 U-0 — bit 15 U1RXREG: UART1 RECEIVE REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0, HSC URX8 bit 8 R-0, HSC URX6 R-0, HSC URX5 R-0, HSC URX4 R-0, HSC URX3 R-0, HSC URX2 R-0, HSC URX1 R-0, HSC UR
PIC24F04KA201 FAMILY 18.0 An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. HIGH/LOW-VOLTAGE DETECT (HLVD) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F04KA201 FAMILY REGISTER 18-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power Ena
PIC24F04KA201 FAMILY 19.0 Note: A block diagram of the A/D Converter is displayed in Figure 19-1. 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 10-Bit High-Speed A/D Converter, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). To perform an A/D conversion: 1.
PIC24F04KA201 FAMILY FIGURE 19-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD VREF+ VR Select VR+ AVSS 16 VR- VREF- Comparator VINH VINL S/H VR- VR+ DAC 10-Bit SAR VINH Conversion Logic MUX A AN0 AN1 AN2 Data Formatting AN1 AN3 VINL ADC1BUF0: ADC1BUFF AN4 AN5 AD1CON1 AN10 AD1CON2 AN11 AD1CON3 AD1CHS MUX B AN12 VBG VBG/2 AN1 VINH AD1PCFG AD1CSSL VINL Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control DS39937B-page 14
PIC24F04KA201 FAMILY REGISTER 19-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HSC R/W-0, HSC SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/
PIC24F04KA201 FAMILY REGISTER 19-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 VCFG2 bit 15 R/W-0 VCFG1 R-0, HSC BUFS bit 7 U-0 — R/W-0 OFFCAL(1) R/W-0 SMPI3 R/W-0 SMPI2 bit 9-8 bit 7 bit 6 bit 5-2 U-0 — U-0 — R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM R/W-0 ALTS bit 0 VCFG<2:0>: Voltage Reference Configuration bits VR+ VR- 000 AVDD AVSS 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin AVDD AVSS 1xx bit 11 bit 10 R/W-0 CSCNA U = Unimple
PIC24F04KA201 FAMILY REGISTER 19-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D in
PIC24F04KA201 FAMILY - REGISTER 19-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 CH0NB bit 15 U-0 — U-0 — U-0 — R/W-0 CH0SB3 R/W-0 CH0SB2 R/W-0 CH0SB1 R/W-0 CH0SB0 bit 8 R/W-0 CH0NA bit 7 U-0 — U-0 — R/W-0 CH0SA4 R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1 R/W-0 CH0SA0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CH0NB: Channel 0 Ne
PIC24F04KA201 FAMILY REGISTER 19-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — PCFG12 PCFG11 PCFG10 — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-10 PCFG<12:10
PIC24F04KA201 FAMILY A/D CONVERSION CLOCK PERIOD(1) EQUATION 19-1: ADCS = TAD –1 TCY TAD = TCY • (ADCS + 1) Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled. FIGURE 19-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC ≤ 250W VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS ≤ 5 kΩ (Typical) RSS ILEAKAGE ±500 nA CHOLD = DAC capacitance = 4.
PIC24F04KA201 FAMILY FIGURE 19-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY NOTES: DS39937B-page 152 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 20.0 The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator module, refer to the “PIC24F Family Reference Manual”, Section 19.
PIC24F04KA201 FAMILY FIGURE 20-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx VIN- COE - VIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CXINB CXINA VIN- Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 11 COE - VBG/2 Cx VIN+ CxOUT Pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 CXINB CVREF DS39937B-page 154 VINVIN+ CxOUT Pin CXINA VIN- COE Cx VIN+ CxOUT Pin Comp
PIC24F04KA201 FAMILY REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTERS R/W-0 CON bit 15 R/W-0 COE R/W-0 CPOL R/W-0 CLPWR U-0 — U-0 — R/W-0 CEVT R-0 COUT bit 8 R/W-0 EVPOL1 bit 7 R/W-0 EVPOL0 U-0 — R/W-0 CREF U-0 — U-0 — R/W-0 CCH1 R/W-0 CCH0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11-10 bit 9 bit 8 bit 7-6 bit 5 bit 4 bit 3-2 bit 1-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is un
PIC24F04KA201 FAMILY REGISTER 20-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC CMIDL — — — — — C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC — — — — — — C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in
PIC24F04KA201 FAMILY 21.0 Note: COMPARATOR VOLTAGE REFERENCE 21.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator Voltage Reference, refer to the “PIC24F Family Reference Manual”, Section 20. “Comparator Voltage Reference Module” (DS39709). Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 21-1).
PIC24F04KA201 FAMILY REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparato
PIC24F04KA201 FAMILY 22.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Measurement Unit, refer to the “PIC24F Family Reference Manual”, Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724).
PIC24F04KA201 FAMILY 22.2 When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected.
PIC24F04KA201 FAMILY REGISTER 22-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enabl
PIC24F04KA201 FAMILY REGISTER 22-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred REGISTER 22-2: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITR
PIC24F04KA201 FAMILY 23.0 SPECIAL FEATURES Note: 23.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Watchdog Timer, High-Level Device Integration and Programming Diagnostics, refer to the individual sections of the “PIC24F Family Reference Manual” provided below: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 36.
PIC24F04KA201 FAMILY REGISTER 23-2: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER R/P-1 U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 IESO — — — — FNOSC2 FNOSC1 FNOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover
PIC24F04KA201 FAMILY REGISTER 23-3: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-1 R/P-1 FCKSM1 FCKSM0 R/P-1 R/P-1 R/P-1 R/P-1 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC R/P-1 R/P-1 POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock M
PIC24F04KA201 FAMILY REGISTER 23-4: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 FWDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) bit 6 WINDIS: Windowed Watchdog Timer Disable b
PIC24F04KA201 FAMILY REGISTER 23-5: R/P-1 MCLRE(1) bit 7 FPOR: RESET CONFIGURATION REGISTER R/P-1 BORV1(2) Legend: R = Readable bit -n = Value at POR R/P-1 BORV0(2) U-0 — P = Programmable bit ‘1’ = Bit is set R/P-1 PWRTEN U-0 — R/P-1 BOREN1 R/P-1 BOREN0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown MCLRE: MCLR Pin Enable bit(1) 1 = MCLR pin enabled; RA5 input pin disabled 0 = RA5 input pin enabled; MCLR disabled BORV<1:0>: Brown-out Reset Enable bits(2) 11 = Br
PIC24F04KA201 FAMILY REGISTER 23-7: FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 R/P-1 U-0 U-0 DSWDTEN DSLPBOR — — R/P-1 R/P-1 R/P-1 R/P-1 DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT enabled 0 = DSWDT disabled bit 6 DSLPBOR: Deep Sleep/Low-Power BOR Enable bit (d
PIC24F04KA201 FAMILY REGISTER 23-8: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bit
PIC24F04KA201 FAMILY 23.2 Watchdog Timer (WDT) For the PIC24F04KA201 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit.
PIC24F04KA201 FAMILY 23.3 Deep Sleep Watchdog Timer (DSWDT) In PIC24F04KA201 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled. It is driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWCKSEL (FDS<4>). The DSWDT can be configured to generate a time-out at 2.1 ms to 25.7 days by selecting the respective postscaler.
PIC24F04KA201 FAMILY NOTES: DS39937B-page 172 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 24.0 DEVELOPMENT SUPPORT 24.
PIC24F04KA201 FAMILY 24.2 MPASM Assembler 24.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC24F04KA201 FAMILY 24.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 24.9 The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC24F04KA201 FAMILY 24.11 PICSTART Plus Development Programmer 24.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC24F04KA201 FAMILY 25.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24F04KA201 FAMILY TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...
PIC24F04KA201 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, D
PIC24F04KA201 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24F04KA201 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws,
PIC24F04KA201 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None
PIC24F04KA201 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR.
PIC24F04KA201 FAMILY NOTES: DS39937B-page 184 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 26.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24F04KA201 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F04KA201 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24F04KA201 FAMILY 26.1 DC Characteristics Voltage (VDD) FIGURE 26-1: PIC24F04KA201 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz 32 MHz Frequency Note: TABLE 26-1: For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz *(VDD – 1.8) + 8 MHz.
PIC24F04KA201 FAMILY TABLE 26-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units DC10 VDD Supply Voltage 1.8 — 3.6 V DC12 VDR RAM Data Retention Voltage(2) 1.5 — — V DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal VSS — 0.
PIC24F04KA201 FAMILY TABLE 26-5: BOR TRIP POINTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym No. DC19 Characteristic Min Typ BOR Voltage on VDD Transition BOR = 00 1.55 2 2.00 V BOR = 01 2.92 3 3.25 V BOR = 10 2.63 2.7 2.92 V BOR = 11 1.75 1.78 2.01 V TABLE 26-6: Conditions Valid for LPBOR and DSBOR DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 1.8V to 3.
PIC24F04KA201 FAMILY TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No. IDD Current DC31 DC31a DC31b DC31c DC31d DC31e DC31f DC31g Note 1: 2: Typical(1) 8 15 Max 28 28 28 28 55 55 55 55 Units μA μA Conditions -40°C +25°C +60°C 1.8V +85°C -40°C +25°C +60°C +85°C 3.3V LPRC (31 kHz) Data in “Typical” column is at 3.
PIC24F04KA201 FAMILY TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param No. Typical(1) Max Units Conditions (2) Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set DC42 200 -40°C DC42a 200 +25°C 94 μA 1.8V DC42b 200 +60°C DC42c 200 +85°C 1 MIPS, FOSC = 2 MHz DC42d 395 -40°C DC42e 395 +25°C 160 μA 3.
PIC24F04KA201 FAMILY TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC60 0.200 -40°C DC60a 0.200 +25°C DC60b 0.025 0.870 μA +60°C DC60c 1.350 +85°C DC60d 0.540 -40°C DC60e DC60f 0.105 0.540 1.
PIC24F04KA201 FAMILY TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC62 0.650 -40°C DC62a 0.650 +25°C 0.450 DC62b 0.650 μA +60°C DC62c 0.650 +85°C DC62d 0.980 -40°C DC62e 0.730 DC62f 0.980 0.
PIC24F04KA201 FAMILY TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC70 0.200 -40°C DC70a 0.200 +25°C DC70b 0.045 0.200 μA +60°C DC70c 0.200 +85°C DC70d 0.200 -40°C DC70e DC70f 0.095 0.200 0.
PIC24F04KA201 FAMILY TABLE 26-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym Characteristic Input Low Voltage(4) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions — — — — I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.
PIC24F04KA201 FAMILY TABLE 26-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL DO10 OSC2/CLKO VOH DO20 DO26 Min Typ(1) Max Units — — 0.4 V IOL = 6.5 mA, VDD = 3.6V — — 0.4 V IOL = 3.5 mA, VDD = 2.0V Conditions Output Low Voltage All I/O Pins DO16 Note 1: Characteristic Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial — — 0.4 V IOL = 8.0 mA, VDD = 3.6V — — 0.
PIC24F04KA201 FAMILY TABLE 26-12: COMPARATOR DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol Characteristic Min Typ Max Units D300 VIOFF Input Offset Voltage* — 20 40 mV D301 VICM Input Common Mode Voltage* 0 — VDD V D302 CMRR Common Mode Rejection Ratio* 55 — — dB Comments * Parameters are characterized but not tested. TABLE 26-13: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS Operating Conditions: 2.
PIC24F04KA201 FAMILY 26.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24F04KA201 family AC characteristics and timing parameters. TABLE 26-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.
PIC24F04KA201 FAMILY FIGURE 26-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS31 OS30 OS31 OS25 CLKO OS41 OS40 TABLE 26-19: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 1.8 to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param Sym No.
PIC24F04KA201 FAMILY TABLE 26-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 3.6V) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
PIC24F04KA201 FAMILY FIGURE 26-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 26-2 for load conditions. TABLE 26-23: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 1.8V to 3.
PIC24F04KA201 FAMILY TABLE 26-24: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 1.8 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V AD05 VREFH Reference Voltage High AVSS + 1.7 — AVSS AVSS – 0.
PIC24F04KA201 FAMILY TABLE 26-25: ADC CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
PIC24F04KA201 FAMILY TABLE 26-26: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max.
PIC24F04KA201 FAMILY NOTES: DS39937B-page 204 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 14-Lead PDIP Example PIC24F04KA200 -I/P e3 0910017 XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead TSSOP Example XXXXXXXX YYWW NNN 24F4KA e3 0910 017 20-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
PIC24F04KA201 FAMILY 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 20-Lead SOIC (.300”) 24F04KA201 -I/SS e3 0910017 Example PIC24F04KA201 -I/SO e3 XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX 0910017 YYWWNNN 20-Lead QFN Example 24F04 KA201 /MQ e3 0910017 XXXXXX XXXXXX XXXXXX YYWWNNN DS39937B-page 206 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY 27.2 Package Details The following sections give the technical details of the packages.
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PIC24F04KA201 FAMILY 20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-120A DS39937B-page 212 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY APPENDIX A: REVISION HISTORY Revision A (February 2009) Original data sheet for the PIC24F04KA201 family of devices. Revision B (May 2009) The title was changed. Section 2.0 “Guidelines for Getting Started with 16-Bit Microcontrollers” was added. Extensive changes to Section 26.0 “Electrical Characteristics”. Minor text edits throughout document. © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY NOTES: DS39937B-page 214 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY INDEX A C A/D C Compilers MPLAB C18 ............................................................. 174 MPLAB C30 ............................................................. 174 Charge Time Measurement Unit. See CTMU. Code Examples Erasing a Program Memory Row, ‘C’ Language Code ............................................ 47 Erasing a Program Memory Row, Assembly Language Code ................................ 46 I/O Port Write/Read .................................................
PIC24F04KA201 FAMILY Deep Sleep BOR (DSBOR) ............................................... 56 Development Support ...................................................... 173 Device Features (Summary) ................................................ 9 Doze Mode ......................................................................... 97 E Electrical Characteristics Absolute Maximum Ratings ..................................... 185 Thermal Operating Conditions .................................
PIC24F04KA201 FAMILY PMD ........................................................................... 36 PORTA ....................................................................... 33 PORTB ....................................................................... 33 SPI ............................................................................. 32 Timer .......................................................................... 31 UART ........................................................................
PIC24F04KA201 FAMILY NOTES: DS39937B-page 218 Preliminary © 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24F04KA201 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC24F04KA201 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 F 04 KA2 01 T - I / SS - XXX Examples: a) Microchip Trademark Architecture PIC24F04KA201-I/MQ: General purpose, 16-Kbyte program memory, 20-pin, Industrial temp., QFN package.
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