Information

© 2006 Microchip Technology Inc. DS80200D-page 3
PIC18F2525/2620/4525/4620
6. Module: ECCP
When monitoring a shutdown condition using a bit
test on the ECCPASE bit (ECCP1AS<7>), or
performing a bit operation on the ECCPASE bit,
the device may produce unexpected results.
Work around
Before performing a bit test or bit operation on the
ECCPASE bit, copy the ECCP1AS register to the
working register and perform the operation there.
By avoiding these operations on the ECCPASE bit
in the ECCP1AS register, the module will operate
normally.
In Example 1, ECCPASE bit operations are
performed on the W register.
Date Codes that pertain to this issue:
All engineering and production devices.
EXAMPLE 1:
7. Module: ECCP
The auto-shutdown source, FLT0, has inverse
polarity from the description in Section 16.4.7
“Enhanced PWM Auto-Shutdown” of the Device
Data Sheet. A logic high-voltage level on FLT0 will
generate a shutdown on CCP1.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
8. Module: ECCP and CCP
The CCP1 and CCP2 configured for PWM mode,
with 1:1 Timer2 prescaler and duty cycle set to the
period minus 1, may result in the PWM output(s)
remaining at a logic low level.
Clearing the PR2 register to select the fastest
period may also result in the output(s) remaining at
a logic low output level.
Work around
To ensure a reliable waveform, verify that the
selected duty cycle does not equal the 10-bit
period minus 1 prior to writing these locations, or
use 1:4 or 1:16 Timer2 prescale. Also, verify the
PR2 register is not written to 00h.
All other duty cycle and period settings will function
as described in the Device Data Sheet.
The ECCP and CCP modules remain capable of
10-bit accuracy.
Date Codes that pertain to this issue:
All engineering and production devices.
MOVF ECCP1AS, W
BTFSC WREG, ECCPASE
BRA SHUTDOWN_ROUTINE