Information

PIC18F2525/2620/4525/4620

42. Module: MSSP

The MSSP configured for SPI mode, the Buffer

Full Status bit, BF (SSPSTAT<0>) should not be

polled in software to determine when the transfer

is complete.

Work around

Copy the SSPSTAT register into a variable and

perform the bit test on the variable. In Example 6,

SSPSTAT is copied into the working register

where the bit test is performed.

EXAMPLE 6:

A second options is to poll the

Master Synchro-

nous Serial Port Interrupt Flag bit, SSPIF

(PIR1<3>). This bit can be polled and will set when

the transfer is complete.

Date Codes that pertain to this issue:

All engineering and production devices.

43. Module: Reset

This version of silicon does not support the func-

tionality described in Note 1 of parameter D002 in

Section 26.1 “DC Characteristics: Supply

Voltage” of the data sheet. The RAM content may

be altered during a Reset event if following

conditions are met.

• Device is accessing RAM.

• Asynchronous Reset (i.e., WDT, BOR or MCLR

occurs when a write operation is being

executed (start of a Q4 cycle).

Work around

None

Date Codes that pertain to this issue:

All engineering and production devices.

loop_MSB:

MOVF SSPSTAT, W

BTFSS WREG, BF

BRA loop_MSB