Information

PIC18F2525/2620/4525/4620
DS80200D-page 10 © 2006 Microchip Technology Inc.
24. Module: EUSART
The EUSART auto-baud feature may periodically
measure the incoming baud rate incorrectly. The
rate of incorrect baud rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
25. Module: EUSART
In Synchronous mode (SYNC = 1) with clock
polarity high (SCKP = 1), the EUSART transmits a
shorter than expected clock on the CK pin for bit 0.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
26. Module: EUSART
In Synchronous mode, EUSART baud rates using
SPBRG values of ‘0’ and ‘1’ may not function
correctly.
Work around
Use another baud rate configuration to generate
the desired baud rate.
Date Codes that pertain to this issue:
All engineering and production devices.
27. Module: EUSART
During an auto-baud operation, the TX pin is tri-
stated. Transceivers which do not provide a pull-up
on the TX signal may cause the bus to become
inadvertently active and prevent additional bus
activity.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
28. Module: MSSP
In an I
2
C system with multiple slave nodes, an
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and the SSPOV bits. In
both situations, the SSPIF bit is not set and an
interrupt will not occur. The device will vector to the
Interrupt Service Routine only if the interrupt is
enabled and an address match occurs.
Work around
The I
2
C slave must clear the SSPOV bit after each
I
2
C event to maintain normal operation.
Date Codes that pertain to this issue:
All engineering and production devices.
29. Module: MSSP
In I
2
C Master mode, the BRG value of ‘0’ may not
work correctly.
Work around
Use a BRG value greater than ‘0’ by setting
SSPADD ≥ ‘1’.
Date Codes that pertain to this issue:
All engineering and production devices.
30. Module: MSSP
In I
2
C Master mode, the RCEN bit is set by soft-
ware to begin data reception and cleared by the
peripheral after a byte is received. After a byte is
received, the device may take up to 80 T
CY to clear
RCEN and 800 T
CY during emulation.
Work around
Single byte receptions are typically not affected,
since the delay between byte receptions typically
is long enough for the RCEN bit to clear. For mul-
tiple byte receptions, the software must wait until
the bit is cleared by the peripheral before the next
byte can be received.
Date Codes that pertain to this issue:
All engineering and production devices.