Information

© 2008 Microchip Technology Inc. DS80224E-page 5
PIC18F2525/2620/4525/4620
14. Module: ECCP
When switching direction in Full-Bridge PWM
mode, the modulated outputs will switch immedi-
ately instead of waiting for the next PWM cycle.
This may generate unexpected short pulses on the
modulated outputs.
Work around
Disable the PWM or set duty cycle to zero prior to
switching directions.
Date Codes that pertain to this issue:
All engineering and production devices.
15. Module: EUSART
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTA register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next
transmission) is not written immediately follow-
ing the setting of TXIF. This is because any
write to the TXSTA register results in a reset of
the baud rate timer which will effect any ongoing
transmission.
Work around
Load TX9D just after TXIF is set, either by polling
TXIF or by writing TX9D at the beginning of the
Interrupt Service Routine, or only write to TX9D
when a transmission is not in progress
(TRMT = 1).
Date Codes that pertain to this issue:
All engineering and production devices.
16. Module: EUSART
When performing back-to-back transmission in 9-bit
mode (TX9D bit in the TXSTA register is set), the
second byte may be corrupted if it is written into
TXREG immediately after the TMRT bit is set.
Work around
Execute a software delay, at least one half the
transmission’s bit time, after TMRT is set and prior
to writing subsequent bytes into TXREG.
Date Codes that pertain to this issue:
All engineering and production devices.
17. Module: Timer1/Timer3
When Timer1 or Timer3 is configured for the
external clock source and the CCPxCON register
is configured with 0x0B (Compare mode, trigger
special event), the timer is not reset on a Special
Event Trigger.
Work around
Modify firmware to reset the Timer registers upon
detection of the compare match condition –
TMRxL and TMRxH.
Date Codes that pertain to this issue:
All engineering and production devices.
18. Module: Timer1/Timer3
When Timer1 or Timer3 is in External Clock
Synchronized mode and the external clock period
is between 1 and 2 TCY, interrupts will occasionally
be skipped.
Work around
Avoid using an external clock with a period (1/
frequency) between 1 and 2 T
CY.
Date Codes that pertain to this issue:
All engineering and production devices.
19. Module: Timer1/Timer3
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
were written.
Work around
Two work arounds are available: 1) Stop Timer1/
Timer3 before writing the TMR1H/TMR3H
registers; 2) Write TMR1L/TMR3L immediately
after writing TMR1H/TMR3H.
Date Codes that pertain to this issue:
All engineering and production devices.