Information

PIC18F2525/2620/4525/4620
DS80224E-page 14 © 2008 Microchip Technology Inc.
41. Module: MSSP
When the MSSP is configured for SPI mode, the
Buffer Full Status bit, BF (SSPSTAT<0>), should
not be polled in software to determine when the
transfer is complete.
Work around
Copy the SSPSTAT register into a variable and
perform the bit test on the variable. In Example 6,
SSPSTAT is copied into the working register
where the bit test is performed.
EXAMPLE 6:
A second option is to poll the Master Synchronous
Serial Port Interrupt Flag bit, SSPIF (PIR1<3>).
This bit can be polled and will set when the transfer
is complete.
Date Codes that pertain to this issue:
All engineering and production devices.
42. Module: Reset
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 26.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
occurs when a write operation is being
executed (start of a Q4 cycle).
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
43. Module: MSSP (I
2
C Slave)
The MSSP module operating in I
2
C, 7-Bit Slave
mode (SSPM3:SSPM0 = 0110) may not send a
NACK bit (/ACK) in response to receiving the slave
address loaded in SSPADD<7:1>. Addresses are
in one of these ranges:
• 0x00 to 0x07
• 0x78 to 0x7F
These addresses were reserved by Philips
®
Semi-
conductors in “The I
2
C Specification”, Version 2.1,
released January 2000. Section 10.1 “Definition of
bits in the first byte” defines the purposes of these
addresses.
This specification can be found at:
http://www.semiconductors.philips.com/i2c
Work around
This version of the silicon does not respond to
slave addresses in the ranges previously listed.
Use either of these work arounds:
• Change the 7-bit slave address in SSPADD to
an address in the range of 0x08 to 0x77.
• Use Revision B silicon. This version of silicon
removes this issue’s addressing restrictions.
Date Codes that pertain to this issue:
All engineering and production devices.
44. Module: MSSP (SPI Slave)
If configured in SPI Slave mode, the MSSP may not
successfully recognize data packets generated by an
external master processor. This applies to all SPI
Slave modes (CKE/CKP = 1 or 0), whether or not
slave select is enabled (SSPM3:SSPM0 = 010x).
Work around
Insert a series resistor between the SPI master
Serial Data Out (SDO) and the corresponding SPI
slave Serial Data In (SDI) input line of the
microcontroller. The required value for the resistor
varies with the application system’s characteristics
and the process variations between the
microcontrollers.
Experimentation and thorough testing is
encouraged.
Date Codes that pertain to this issue:
All engineering and production devices.
loop_MSB:
MOVF SSPSTAT, W
BTFSS WREG, BF
BRA loop_MSB