Information

PIC18F2525/2620/4525/4620
DS80224E-page 12 © 2008 Microchip Technology Inc.
33. Module: EUSART
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREG, are trans-
ferred to the TSR during the transmission of a Stop
bit. For this to occur, three things must happen in
the same instruction cycle:
• TXREG is written to;
• the baud rate counter overflows (at the end of
the bit period); and
• a Stop bit is being transmitted (shifted out of
TSR).
Work around
If possible, do not use the module’s double buffer
capability. Instead, load the TXREG register when
the TRMT bit (TXSTA<1>) is set, indicating the
TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, then load TXREG
immediately after TXIF is set or wait 1-bit time after
TXIF is set. Both solutions prevent writing TXREG
while a Stop bit is transmitted. Note that TXIF is set
at the beginning of the Stop bit transmission.
If transmission is intermittent, then do the
following:
• Wait for the TRMT bit to be set before
loading TXREG
• Alternatively, use a free timer resource to
time the baud period. Set up the timer to
overflow at the end of Stop bit, then start the
timer when you load the TXREG. Do not
load the TXREG when timer is about to
overflow.
Date Codes that pertain to this issue:
All engineering and production devices.
34. Module: EUSART
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTA<0>) is not modified immediately after the
RCIDL bit (BAUDCON<6>) is set.
Work around
Write to TX9D only when a reception is not in
progress (RCIDL = 1). Since there is no interrupt
associated with RCIDL, it must be polled in
software to determine when TX9D can be
updated.
Date Codes that pertain to this issue:
All engineering and production devices.
35. Module: EUSART
After the last received byte has been read from the
EUSART receive buffer, RCREG, the value is no
longer valid for subsequent read operations.
Work around
The RCREG register should only be read once for
each byte received. After each byte is received
from the EUSART, store the byte into a user vari-
able. To determine when a byte is available to read
from RCREG, poll the RCIDL bit (BAUDCON<6>)
for a low to high transition, or use the EUSART
receive interrupt, RCIF (PIR1<5>).
Date Codes that pertain to this issue:
All engineering and production devices.
36. Module: EUSART
With the auto-wake-up option enabled by setting
the WUE (BAUDCON<1>) bit, the RCIF
(PIR1<5>) bit will become set on a high-to-low
transition on the RX pin. However, the WUE bit
may not clear within 1 T
CY of a low-to-high transi-
tion on RX. While the WUE bit is set, reading the
receive buffer, RCREG, will not clear the RCIF
interrupt flag. Therefore, the first opportunity to
automatically clear RCIF by reading RCREG may
take longer than expected.
Work around
There are two work arounds available:
1. Clear the WUE bit in software after the wake-
up event has occurred prior to reading the
receive buffer, RCREG.
2. Poll the WUE bit and read RCREG after the
WUE bit is automatically cleared.
Date Codes that pertain to this issue:
All engineering and production devices.
Note: RCIF can only be cleared by reading
RCREG