Information

© 2008 Microchip Technology Inc. DS80220J-page 9
PIC18F2455/2550/4455/4550
20. Module: EUSART
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTA<0>) is not modified immediately after the
RCIDL bit (BAUDCON<6>) is set.
Work around
Write to TX9D only when a reception is not in prog-
ress (RCIDL = 1). Since there is no interrupt asso-
ciated with RCIDL, it must be polled in software to
determine when TX9D can be updated.
Date Codes that pertain to this issue:
All engineering and production devices.
21. Module: EUSART
After the last received byte has been read from the
EUSART receive buffer, RCREG, the value is no
longer valid for subsequent read operations.
Work around
The RCREG register should only be read once for
each byte received. After each byte is received
from the EUSART, store the byte into a user vari-
able. To determine when a byte is available to read
from RCREG, poll the RCIDL bit (BAUDCON<6>)
for a low-to-high transition, or use the EUSART
Receive Interrupt Flag, RCIF (PIR1<5>).
Date Codes that pertain to this issue:
All engineering and production devices.
22. Module: EUSART
With the auto-wake-up option enabled by setting
the WUE bit (BAUDCON<1>), the RCIF
(PIR1<5>) bit will become set on a high-to-low
transition on the RX pin. However, the WUE bit
may not clear within 1 T
CY of a low-to-high transi-
tion on RX. While the WUE bit is set, reading the
receive buffer, RCREG, will not clear the RCIF
interrupt flag. Therefore, the first opportunity to
automatically clear RCIF by reading RCREG may
take longer than expected.
Work around
There are two workarounds available:
1. Clear the WUE bit in software, after the wake-
up event has occurred, prior to reading the
receive buffer, RCREG.
2. Poll the WUE bit and read RCREG after the
WUE bit is automatically cleared.
Date Codes that pertain to this issue:
All engineering and production devices.
23. Module: Timer1
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH
registers. The timers increment and set the
interrupt flags as expected. The timer registers can
also be written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
(T1CON<7>).
2. Use the internal clock synchronization option
by clearing the T1SYNC
bit (T1CON<2>).
Date Codes that pertain to this issue:
All engineering and production devices.
24. Module: Reset
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 28.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or
MCLR
) occurs when a write operation is being
executed (start of a Q4 cycle) or if a RESET
instruction is executed and immediately
followed by a RETURN instruction.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
25. Module: ECCP (PWM Mode)
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM
output may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• a non-zero dead-band delay is specified
(PDC6:PDC0 > 0); and
• the duty cycle has a value of 0 through 3, or
4n + 3 (n ≥ 1).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
Note: RCIF can only be cleared by reading
RCREG.