Information

© 2008 Microchip Technology Inc. DS80220J-page 7
PIC18F2455/2550/4455/4550
11. Module: PORTD
Each of the PORTD pins has a weak internal pull-up.
A single control bit, RDPU (PORTE<7>), can turn on
all the pull-ups. After the pull-up has been enabled
(PORTE<7> = 1), any access to the PORTE register
would cause the RDPU control bit to clear, except
those that write a '1' to PORTE<7>.
Work around
Reassert RDPU after each and every access to
the PORTE register, except those that write a ‘1’ to
PORTE<7>, or use external pull-ups.
Date Codes that pertain to this issue:
All engineering and production devices.
12. Module: Module: MSSP
The I
2
C™ slave address masking feature is not
supported, therefore, SSPCON2 register bits,
ADMSK<5:1>, do not exist in I
2
C Slave mode.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
13. Module: EUSART
In the BAUDCON register, bits RXDTP and TXCKP
do not exist. BAUDCON bit 4 is defined instead as
SCKP and has the following definition:
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode
:
Unused in this mode.
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
14. Module: USB
The Ping-Pong Buffer mode in which the ping-pong
buffers are enabled for Endpoints 1 to 15
(UCFG<PPB1:PPB0> = 11) is not supported.
Work around
Use other Ping-Pong Buffer modes.
Date Codes that pertain to this issue:
All engineering and production devices.
15. Module: MSSP
The MSSP configured in SPI Slave mode will
generate a write collision if SSPBUF is updated and
the previous SSPBUF contents have not been
transferred
to the shift register.
Re-initializing the MSSP by clearing and setting the
SSPEN (SSPCON1<5>) bit prior to rewriting
SSPBUF will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify whether the previous contents were
transferred by reading the BF (SSPSTAT<0>) bit. If
the previous byte has not been transferred, update
SSPBUF and clear the WCOL (SSPCON1<7>) bit if
necessary.
Date Codes that pertain to this issue:
All engineering and production devices.
16. Module: MSSP
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.