Information

© 2008 Microchip Technology Inc. DS80220J-page 11
PIC18F2455/2550/4455/4550
29. Module: EUSART
The EUSART auto-baud feature may periodically
measure the incoming baud rate incorrectly. The
rate of incorrect baud-rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
30. Module: ADC
When the A/D clock source is selected as 2 TOSC
or RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the E
IL (Integral Linearity
Error) and E
DL (Differential Linearity Error) may
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select a different A/D clock source (4 TOSC,
8T
OSC, 16 TOSC, 32 TOSC, 64 TOSC) and avoid
selecting the 2 T
OSC or RC modes.
Date Codes that pertain to this issue:
All engineering and production devices.
31. Module: Brown-out Reset (BOR)
If either the HLVD or USB modules are enabled,
clearing the SBOREN bit (RCON<6>) when the soft-
ware controlled BOR feature is enabled
(BOREN1:BOREN0 = 01) may cause a Brown-out
Reset (BOR) event.
Work around
Before clearing the SBOREN bit, temporarily
disable the HLVD and USB modules.
Date Codes that pertain to this issue:
All engineering and production devices.
32. Module: MSSP
When operated in I
2
C™ Master mode, the I
2
C
baud rate may be somewhat slower than predicted
by the following formula:
Work around
If the target application is sensitive to the baud rate
and requires more precision, the SSPADD value
can be adjusted to compensate.
If this work around is going to be used, it is recom-
mended that the firmware first check the Revision
ID by reading the DEVID1 value at address
3FFFFEh. Silicon revisions B6 and B7 will match
the I
2
C baud rate predicted by the given formula.
Date Codes that pertain to this issue:
All engineering and production devices.
I
2
C Master mode, clock
F
OSC
4 SSPADD 1+()•
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