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PIC18F2455/2550/4455/4550

The PIC18F2455/2550/4455/4550 parts you have

received conform functionally to the Device Data Sheet

(DS39632D), except for the anomalies described

below. Any Data Sheet Clarification issues related to

the PIC18F2455/2550/4455/4550 will be reported in a

separate Data Sheet errata. Please check the

Microchip web site for any existing issues.

The following silicon errata apply only to

PIC18F2455/2550/4455/4550 devices with these

Device/Revision IDs:

1. Module: EUSART

When performing back-to-back transmission in

9-bit mode (TX9D bit in the TXSTA register is

set), an ongoing transmission’s timing can be

corrupted if the TX9D bit (for the next transmis-

sion) is not written immediately following the

setting of TXIF. This is because any write to the

TXSTA register results in a reset of the Baud

Rate Generator which will effect any ongoing

transmission.

Work around

Load TX9D just after TXIF is set, either by polling

TXIF or by writing TX9D at the beginning of the

Interrupt Service Routine, or only write to TX9D

when a transmission is not in progress

(TRMT = 1).

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: Timer1/Timer3

When Timer1/Timer3 is operating in 16-bit mode

and the prescale setting is not 1:1, a write to the

TMR1H/TMR3H Buffer registers may lengthen the

duration of the period between the increments of

the timer for the period in which TMR1H/TMR3H

were written.

Work around

Two work arounds are available: 1) Stop Timer1/

Timer3 before writing the TMR1H/TMR3H regis-

ters; 2) Write TMR1L/TMR3L immediately after

writing TMR1H/TMR3H.

Date Codes that pertain to this issue:

All engineering and production devices.

3. Module: MSSP

In Slave Transmit mode, when a transmission is

initiated, the SSPBUF register may be written for

up to 10 T

CY before additional writes are blocked.

The data transfer may be corrupted if SSPBUF is

written during this time.

The WCOL bit is set any time an SSPBUF write

occurs during a transfer.

Work around

Avoid writing SSPBUF until the data transfer is

complete, indicated by the setting of the SSPIF bit

(PIR1<3>).

Verify the WCOL bit (SSPCON1<7>) is clear after

writing SSPBUF to ensure any potential transfer in

progress is not corrupted.

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F2455 0001 0010 011 0 0010

PIC18F2550 0001 0010 010 0 0010

PIC18F4455 0001 0010 001 0 0010

PIC18F4550 0001 0010 000 0 0010

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in binary in the

format “DEVID2 DEVID1”.

PIC18F2455/2550/4455/4550 Rev. A3 Silicon Errata

Summary of content (14 pages)

PAGE 1
PIC18F2455/2550/4455/4550 PIC18F2455/2550/4455/4550 Rev. A3 Silicon Errata The PIC18F2455/2550/4455/4550 parts you have received conform functionally to the Device Data Sheet (DS39632D), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2455/2550/4455/4550 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues.
PAGE 2
PIC18F2455/2550/4455/4550 4. Module: Interrupts If an interrupt occurs during a two-cycle instruction that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register and upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register.
PAGE 3
PIC18F2455/2550/4455/4550 2. C Language Programming: The exact work around depends on the compiler in use. Please refer to your C compiler documentation for details. If using the Microchip MPLAB® C18 C Compiler, define both high and low priority interrupt handler functions as “low priority” by using the pragma interruptlow directive. This directive instructs the compiler to not use the RETFIE FAST instruction.
PAGE 4
PIC18F2455/2550/4455/4550 An optimized C18 version is also provided in Example 3. This example illustrates how it reduces the instruction cycle count from 10 cycles to 3: EXAMPLE 3: #pragma code high_vector_section=0x8 void high_vector (void) { _asm CALL high_vector_branch, 1 _endasm } void high_vector_branch (void) { _asm POP GOTO high_isr _endasm } #pragma interrupt high_isr void high_isr (void) { ... } DS80220J-page 4 © 2008 Microchip Technology Inc.
PAGE 5
PIC18F2455/2550/4455/4550 5. Module: ECCP When monitoring a shutdown condition using a bit test on the ECCPASE bit (ECCP1AS<7>), or performing a bit operation on the ECCPASE bit, the device may produce unexpected results. Work around Before performing a bit test or bit operation on the ECCPASE bit, copy the ECCP1AS register to the working register and perform the operation there. 7.
PAGE 6
PIC18F2455/2550/4455/4550 8. Module: A/D 2. Perform a conversion on a known voltage reference voltage and adjust the A/D result in software. 3. Increase system clock speed to 48 MHz and adjust A/D settings accordingly. Higher system clock frequencies decrease offset error. The A/D offset is greater than the specified limit in Table 28-28 of the Device Data Sheet. The updated conditions and limits are shown in bold text in Table 1.
PAGE 7
PIC18F2455/2550/4455/4550 11. Module: PORTD 14. Module: USB Each of the PORTD pins has a weak internal pull-up. A single control bit, RDPU (PORTE<7>), can turn on all the pull-ups. After the pull-up has been enabled (PORTE<7> = 1), any access to the PORTE register would cause the RDPU control bit to clear, except those that write a '1' to PORTE<7>. The Ping-Pong Buffer mode in which the ping-pong buffers are enabled for Endpoints 1 to 15 (UCFG = 11) is not supported.
PAGE 8
PIC18F2455/2550/4455/4550 17. Module: MSSP 19. Module: EUSART It has been observed that following a Power-on Reset, I2C mode may not initialize properly by just configuring the SCL and SDA pins as either inputs or outputs. This has only been seen in a few unique system environments. In rare situations, one or more extra zero bytes have been observed in a packet transmitted by the module operating in Asynchronous mode.
PAGE 9
PIC18F2455/2550/4455/4550 20. Module: EUSART 23. Module: Timer1 In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTA<0>) is not modified immediately after the RCIDL bit (BAUDCON<6>) is set. In 16-Bit Asynchronous Counter mode (with or without use of the Timer1 oscillator), the TMR1H and TMR3H buffers do not update when TMRxL is read. Work around This issue only affects reading the TMRxH registers.
PAGE 10
PIC18F2455/2550/4455/4550 26. Module: MSSP With MSSP in SPI Master mode, FOSC/64 or Timer2/2 clock rate and CKE = 0, a write collision may occur if SSPBUF is loaded immediately after the transfer is complete. A delay may be required after the MSSP Interrupt Flag bit, SSPIF, is set or the Buffer Full bit, BF, is set, and before writing SSPBUF. If the delay is insufficiently short, a write collision may occur as indicated by the WCOL bit being set. 28.
PAGE 11
PIC18F2455/2550/4455/4550 29. Module: EUSART 31. Module: Brown-out Reset (BOR) The EUSART auto-baud feature may periodically measure the incoming baud rate incorrectly. The rate of incorrect baud-rate measurements will depend on the frequency of the incoming synchronization byte and the system clock frequency. If either the HLVD or USB modules are enabled, clearing the SBOREN bit (RCON<6>) when the software controlled BOR feature is enabled (BOREN1:BOREN0 = 01) may cause a Brown-out Reset (BOR) event.
PAGE 12
PIC18F2455/2550/4455/4550 REVISION HISTORY Rev A Document (11/2004) Original version of this document. Includes silicon issues 1 (EUSART), 2 (Timer1/Timer3), 3 (MSSP), 4 (Interrupts), 5-7 (ECCP), 8 (A/D) and 9 (DC Characteristics (BOR)). Rev B Document (07/2005) Added silicon issue 10 (USB). Rev C Document (11/2005) Updated issue 4 (Interrupts) and added silicon issue 11 (PORTD). Rev D Document (03/2006) Added silicon issues 12 (MSSP), 13 (EUSART) and 14 (USB).
PAGE 13
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 14
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