Information

PIC18F2455/2550/4455/4550
DS80478A-page 8 © 2009 Microchip Technology Inc.
8. Module: A/D
The A/D offset is greater than the specified limit in
Table 28-8 of the Device Data Sheet. The updated
conditions and limits are shown in bold text in
Table 28-8.
Work around
Any of three work arounds may be used.
• Configure the A/D to use the V
REF+ and VREF-
pins for the voltage references. This is done
by setting the VCFG<1:0> bits
(ADCON1<5:4>).
• Perform a conversion on a known voltage
reference voltage and adjust the A/D result in
software.
• Increase system clock speed to 48 MHz and
adjust A/D settings accordingly. Higher
system clock frequencies decrease offset
error.
TABLE 28-8: A/D CONVERTER CHARACTERISTICS:PIC18F2455/2550/4455/4550 (INDUSTRIAL)
PIC18LF2455/2550/4455/4550 (INDUSTRIAL)
Affected Silicon Revisions
9. Module: DC Characteristics (BOR)
When the trip point for BORV<1:0> = 11, the val-
ues for parameter D005 (V
BOR) in Section 28.1
“DC Characteristics” of the Device Data Sheet
are not applicable as the device may reset below
the minimum operating voltage for the device.
Work around
None.
Affected Silicon Revisions
10. Module: USB
When an IN endpoint is owned by USB SIE and
the UCON register’s PKTDIS bit is set, if a USB
NAK event occurs on the IN endpoint before the
PKTDIS bit is clear, then after the PKTDIS is clear,
the pending IN endpoint will send out more bytes
than expected. For example, if configured to send
out 8 bytes, the SIE would actually send out
12 bytes of data.
Work around
The PKTDIS bit is set when a USB control transfer
setup packet is received. Clear this bit as soon as
possible, particularly before turning over any IN
endpoint ownership to the SIE.
Affected Silicon Revisions
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
A06A E
OFF Offset Error — — <±2.0 LSb VREF = VREF+ and VREF-
A06 E
OFF Offset Error — — <±3.5 LSb VREF = VSS and VDD
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X