Information

© 2009 Microchip Technology Inc. DS80478A-page 7
PIC18F2455/2550/4455/4550
5. Module: ECCP
When monitoring a shutdown condition using a
bit test on the ECCPASE bit (ECCP1AS<7>) or
performing a bit operation on the ECCPASE bit,
the device may produce unexpected results.
Work around
Before performing a bit test or bit operation on
the ECCPASE bit, copy the ECCP1AS register to
the working register and perform the operation
there.
By avoiding these operations on the ECCPASE
bit in the ECCP1AS register, the module will
operate normally.
In Example 4, ECCPASE bit operations are
performed on the W register.
EXAMPLE 4: ECCPASE OPERATION
Affected Silicon Revisions
6. Module: ECCP
When the CCP1 auto-shutdown feature is config-
ured for automatic restart (PRSEN bit
(ECCP1DEL<7>) = 1), the pulse terminates
immediately in a shutdown event. In addition, the
pulse may restart within the period, if the shut-
down condition expires. This may result in the
generation of short pulses on the PWM output(s).
Work around
Configure the auto-shutdown for software
restart by clearing the PRSEN bit
(ECCP1DEL<7>). The PWM can be re-enabled,
after the shutdown condition expires, by clearing
the ECCPASE bit (ECCP1AS<7>).
Affected Silicon Revisions
7. Module: ECCP
When operating either Timer1 or Timer3 as a
counter with a prescale value other than 1:1 and
operating the ECCP in Compare mode with the
Special Event Trigger (CCP1CON bits,
CCP1M<3:0> = 1011), the Special Event Trigger
Reset of the timer occurs as soon as there is a
match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
This differs from the PIC18F452, where the
Special Event Trigger Reset of the timer occurs
on the next rollover of the prescale counter after
the match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
Work around
To achieve the same timer Reset period on the
PIC18F4550 family as the PIC18F452 family for a
given clock source, add 1 to the value in
CCPR1H:CCPR1L. In other words, if
CCPR1H:CCPR1L = x for the PIC18F452, to
achieve the same Reset period on the
PIC18F4550 family, CCPR1H:CCPR1L = x + 1,
where the prescale is 1, 2, 4 or 8 depending on the
T1CKPS<1:0> bit values.
Affected Silicon Revisions
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X
MOVF ECCP1AS, W
BTFSC WREG, ECCPASE
BRA SHUTDOWN_ROUTINE
A3 B4 B5 B6 B7
X