Information

PIC18F2455/2550/4455/4550
DS80478A-page 4 © 2009 Microchip Technology Inc.
Silicon Errata Issues
1. Module: EUSART
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTA register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next transmis-
sion) is not written immediately following the
setting of TXIF. This is because any write to the
TXSTA register results in a reset of the Baud
Rate Generator which will effect any ongoing
transmission.
Work around
Load TX9D just after TXIF is set, either by polling
TXIF or by writing TX9D at the beginning of the
Interrupt Service Routine, or only write to TX9D
when a transmission is not in progress
(TRMT = 1).
Affected Silicon Revisions
2. Module: Timer1/3
When Timer1/3 is operating in 16-bit mode and
the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen
the duration of the period between the incre-
ments of the timer for the period in which
TMR1H/TMR3H were written.
Work around
Either of two work arounds can be used:
• Stop Timer1/Timer3 before writing the
TMR1H/TMR3H registers
• Write TMR1L/TMR3L immediately after
writing TMR1H/TMR3H
Affected Silicon Revisions
3. Module: MSSP
In Slave Transmit mode, when a transmission is
initiated, the SSPBUF register may be written for
up to 10 TCY before additional writes are blocked.
The data transfer may be corrupted if SSPBUF is
written during this time.
The WCOL bit is set any time an SSPBUF write
occurs during a transfer.
Work around
Avoid writing SSPBUF until the data transfer is
complete, indicated by the setting of the SSPIF bit
(PIR1<3>).
To ensure any potential transfer in progress is not
corrupted, verify that the WCOL bit
(SSPCON1<7>) is clear after writing SSPBUF.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B7).
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X