Information

© 2009 Microchip Technology Inc. DS80478A-page 3
PIC18F2455/2550/4455/4550
BOR HLVD or USB 30. Clearing SBOREN can cause BOR X
MSSP I
2
C mode 31. I
2
C baud rate not meeting formula X X X
MSSP SPI slave 32. SPI slave not meeting timing parameter 70 X X X X
Timer1/3
Eight-Bit
Async
33. Need delay between consecutive writes X
BOR Threshold 34. Certain conditions move BOR threshold X X X
BOR Threshold 35. Table reads can move BOR threshold X
EUSART
Synch
Master
36. Synchronous master mode, DT data changes X X
MSSP SPI Slave 37. SPI Slave needs a series resistor X X X
MSSP SPI modes 38. SPI modes, incoming data not received if BF set X X
MSSP I
2
C Slave 39.
With I
2
C slave reception, need to read data
promptly
XXXXX
MSSP I
2
C Master 40.
In I
2
C Master mode, narrow clock width upon
slave clock stretch
XX
EUSART Interrupts 41.
If interrupts are enabled, 2 T
CY delay needed
after re-enabling the module
XXXX
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A3 B4 B5 B6 B7
Note 1: Only those issues indicated in the last column apply to the current silicon revision.