Information

PIC18F2455/2550/4455/4550

10. Module: MSSP (SPI Master)

In Section 19.3.5, “Master Mode,” the following

content is added:

When used in Timer2 Output/2 mode, the SPI bit

rate can be configured using the PR2 Period

To operate in this mode, firmware must first ini-

tialize and enable the Timer2 module before it

can be used with the MSSP. Once enabled, the

Timer2 module is free-running and mostly

independent of the MSSP module.

Writing to the SSPBUF register will not clear the

current TMR2 value in hardware. This can result

in an unpredictable SPI transmit MSb bit width,

depending on how close the TMR2 register was

to the PR2 match condition at the moment that

the firmware wrote to SSPBUF.

To avoid the unpredictable MSb bit width, initial-

ize the TMR2 register to a known value when

writing to SSPBUF. An example procedure,

which provides predictable bit widths (only

needed in the Timer2/2 mode), is given in

Example 10.

EXAMPLE 10: LOADING SSPBUF WITH THE TIMER2/2 CLOCK MODE

TransmitSPI:

BCF PIR1, SSPIF ;Make sure interrupt flag is clear (may have been set from previous

;transmission)

MOVF SSPBUF, W ;Perform read, even if the data in SSPBUF is not important

MOVWF RXDATA ;Save previously received byte in user RAM, if the data is meaningful

BCF T2CON, TMR2ON ;Turn off timer when loading SSPBUF

CLRF TMR2 ;Set timer to a known state

MOVF TXDATA, W ;WREG = Contents of TXDATA (user data to send)

MOVWF SSPBUF ;Load data to send into transmit buffer

BSF T2CON, TMR2ON ;Start timer to begin transmission

WaitComplete: ;Loop until data has finished transmitting

BTFSS PIR1, SSPIF ;Interrupt flag set when transmit is complete

BRA WaitComplete