Information

PIC18F2455/2550/4455/4550
DS80478A-page 2 © 2009 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A3 B4 B5 B6 B7
EUSART
Nine-Bit
mode
1. Back-to-back timing transmit corruption X
Timer1/3
Sixteen-Bit
mode
2. Write to TMR1H/3H may lengthen duration X
MSSP
Slave
Transmit
3. Slave transmit, 10 T
CY not blocked X
Interrupts
Two-Cycle
Instructions
4. Special considerations for interrupt context save X
ECCP
ECCPASE
Bit
5. Do not use bit-wise operations on ECCPASE X
ECCP Auto-Restart 6.
Immediate restart upon shutdown source
removal
X
ECCP
Special Event
Trigger
7.
Compare mode, Special Event Trigger not like
PIC18F452
X
ADC Offset Error 8. Offset greater than data sheet X
BOR V
BOR 9. ‘11’ setting below minimum operating voltage X
USB
SIE IN
Endpoint
10. PKTDIS set, NAK, four extra bytes sent X
PORTD
RDPU
Control Bit
11. Access to PORTE causes RDPU to clear X
MSSP
Slave
Addressing
12. I
2
C™ slave address masking not implemented X
EUSART
BAUDCON
Register
13. RXDTP, TXCKP do not exist X
USB
Ping-Pong
Buffer
14. Ping-Pong mode ‘11’ not supported X
MSSP
SPI Slave
mode
15. SPI slave write collision X
MSSP SPI mode 16. SPI SDO output may change X
MSSP I
2
C™ mode 17. I
2
C pins may not initialize properly X
MSSP SPI mode 18. In SPI mode, do not poll BF bit X
EUSART Async mode 19. Extra zero bytes in Async mode X
EUSART Async mode 20. Data corruption in 9-bit Async full-duplex X
EUSART
Receive
Buffer
21. RCREG not valid for subsequent reads X
EUSART
Auto
Wake-up
22. WUE bit not clearing promptly X
Timer1/3 16-Bit Async 23. 16-Bit Async mode, TMR1H/3H not updated X
Reset RAM 24. Asynch Reset can alter RAM X
ECCP PWM mode 25. Dead-band delay incorrect X X X X X
MSSP
SPI Master
mode
26.
SPI master, write collision for F
OSC/64 and
Timer2/2
XXXXX
MSSP I
2
C mode 27. Unaddressed I
2
C slave node may respond X
EUSART Auto-Baud 28. Auto-baud sometimes does not work X
ADC
2T
OSC or RC
Clock
29. E
IL, EDL, not meeting data sheet at 511/512 X X X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.