Information

© 2009 Microchip Technology Inc. DS80478A-page 19
PIC18F2455/2550/4455/4550
2. Module: Timer1
The following text, Section 12.7 “Considerations
in Asynchronous Counter Mode”, is new. It
defines the proper method to update the TMR1
registers in Asynchronous mode.
Section 12.7 is located after Section 12.6 “Using
Timer1 as a Real-Time Clock” in the data sheet.
12.7 Considerations in Asynchronous
Counter Mode
Following a Timer1 interrupt and an update to the
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed fol-
lowing a later Timer1 increment. This can be done by
monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L reg-
ister pair while the clock is low, or one-half of the period
of the clock source. Assuming that Timer1 is being
used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator; in this case, one-half
period of the clock is 15.25 μs.
The Real-Time Clock application code in Example 12-1
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
(Example 12-1 appears on page 18 of this errata.)
3. Module: Universal Serial Bus (USB)
In Section 17.2.2.8 “Internal Regulator,” the fol-
lowing corrections should be noted (changes and
added text appear in bold for the purposes of this
errata):
• In the second paragraph, the first sentence is
corrected to read, “The regulator is disabled by
default and can be enabled through the
VREGEN Configuration bit.”
The sentence originally stated, “The regulator is
enabled by default and can be disabled through
the VREGEN Configuration bit.”
• In the final note box of the section, Note 2 is
corrected to read, “V
DD must be greater than or
equal to V
USB at all times, even with the
regulator disabled.”
The sentence originally stated, “V
DD must be
greater than V
USB at all times, even with the
regulator disabled.”
4. Module: Master Synchronous Serial Port
(MSSP)
In Section 19.3.5 “Master Mode,” the second
paragraph of the second column is corrected to
read, “This allows a maximum data rate (at
48 MHz) of 12.00 Mbps.”
The sentence originally stated, “This allows a
maximum data rate (at 48 MHz) of 2.00 Mbps.”
5. Module: 10-Bit Analog-to-Digital (A/D)
Converter
In Register 21-1, the display and the detailed bit
description for bit 5 is corrected to “VCFG1”,
rather than “VCFG0”. All other bit 5 displays and
descriptions are correct in the Device Data Sheet.
6. Module: Special Features of the CPU
In Section 25.9.1 “Dedicated ICD/ICSP Port”,
the second sentence of the fourth paragraph is
corrected to state, “When VIHH is seen on the
MCLR
/VPP/RE3 pin, the state of the ICRST/ICVPP
pin is ignored”. This refers to the high-voltage
programming voltage level for ICSP™ (DC
Specification D110).
The sentence originally stated, “When V
IH is seen
on the MCLR
/VPP/RE3 pin, the state of the ICRST/
ICV
PP pin is ignored”. That incorrectly referred to
the maximum input voltage tolerated by the pin as
an I/O (DC specification D040).