Information

© 2009 Microchip Technology Inc. DS80478A-page 17
PIC18F2455/2550/4455/4550
39. Module: MSSP (I
2
C™ Slave)
When configured for I
2
C™ slave reception, the
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read after the SSPIF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPCON2<0>).
• Each time the SSPIF is set, read the SSPBUF
before the first rising clock edge of the next byte
being received.
Affected Silicon Revisions
40. Module: MSSP (I
2
C™ Master)
When in I
2
C Master mode, if the slave performs
clock stretching, the first clock pulse after the slave
releases the SCL line may be narrower than the
configured clock width. This may result in the slave
missing the first clock in the next transmission/
reception.
Work around
The clock pulse will be the normal width if the slave
does not perform clock stretching.
Affected Silicon Revisions
41. Module: EUSART
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTAx<7> = 0)
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
after setting SPEN = 1
Work around
Add a 2 TCY delay after any instruction that re-
enables the EUSART module (sets SPEN = 1).
See Example 9.
EXAMPLE 9: RE-ENABLING A EUSART MODULE
Affected Silicon Revisions
A3 B4 B5 B6 B7
XXXX
X
A3 B4 B5 B6 B7
X
X
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf RCSTA1, SPEN ;or RCSTA2 if EUSART2
nop ;1 Tcy delay
nop ;1 Tcy delay (two total)
;CPU may now execute 2 cycle instructions
A3 B4 B5 B6 B7
XXX
X