Information

© 2009 Microchip Technology Inc. DS80478A-page 15
PIC18F2455/2550/4455/4550
33. Module: Timer1/3
For Timer1 or Timer3, if the TMRxH and TMRxL
registers are written to in consecutive instruction
cycles, the timer may not be updated with the
correct value if it is configured for externally
clocked, 8-Bit Asynchronous mode (T1CON<7:0>
or T3CON<7:0> = 0xxx x111).
For the purposes of this issue, instructions that
directly affect the contents of the Timer registers
are considered to be writes. This includes CLRF,
SETF and MOVF instructions.
Work around
Insert a delay of one or more instruction cycles
between writes to TMRxH and TMRxL. This delay
can be a NOP, or any instruction that does not
access the Timer registers (Example 6).
EXAMPLE 6: TIMER1/3 – CONSECUTIVE
WRITES
Affected Silicon Revisions
34. Module: Resets (BOR)
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the Device Data Sheet (parameter D005).
The BOR threshold has been observed to increase
with high device operating frequencies, some table
read operations and heavy loading on the USB
voltage regulator. When all of these conditions are
present, BOR has been observed with V
DD
20 percent higher than the VBOR value specified
for a given BORV<1:0> setting.
The BOR threshold may decrease under other
conditions, such as during Sleep, where it may not
occur until V
DD is 120 mV below the specified
minimums.
Work around
None.
Affected Silicon Revisions
35. Module: Resets (BOR)
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the Device Data Sheet (parameter D005).
The BOR threshold has been observed to increase
with some table read operations. BOR has been
observed with 7 percent higher V
DD than the VBOR
value specified for a given BORV<1:0> setting.
Work around
None.
Affected Silicon Revisions
36. Module: EUSART
In Synchronous Master mode, while transmitting
the Most Significant data bit, the data line (DT)
may change state before the bit finishes transmit-
ting. If the receiver samples the data line later than
0.5 bit times + 1.5 T
CY (of the master) after the
starting edge of the MSb, the bit may be read
incorrectly.
Work around
None.
Affected Silicon Revisions
37. Module: MSSP (SPI Slave)
If configured in SPI Slave mode, the MSSP may not
successfully recognize data packets generated by an
external master processor. This applies to all SPI
Slave modes (CKE/CKP = 1 or 0), whether or not
slave select is enabled (SSPM<3:0> = 010x).
Work around
Insert a series resistor between the SPI master
Serial Data Out (SDO) and the corresponding SPI
slave Serial Data In (SDI) input line of the
microcontroller. The required value for the resistor
varies with the application system’s characteristics
and the process variations between the
microcontrollers.
Experimentation and thorough testing are
encouraged.
Affected Silicon Revisions
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
XXX
CLRF TMR1H
MOVLW T1Offset ; 1 Tcy delay
MOVWF TMR1L
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
XX
A3 B4 B5 B6 B7
XXX