Information

PIC18F2455/2550/4455/4550
DS80478A-page 14 © 2009 Microchip Technology Inc.
31. Module: MSSP
When operated in I
2
C™ Master mode, the I
2
C
baud rate may be somewhat slower than predicted
by the following formula:
Work around
If the target application is sensitive to the baud rate
and requires more precision, the SSPADD value
can be adjusted to compensate.
If this work around is going to be used, it is recom-
mended that the firmware first check the Revision
ID by reading the DEVID1 value at address,
3FFFFEh. Silicon revisions, B6 and B7, will match
the I
2
C baud rate predicted by the given formula.
Affected Silicon Revisions
32. Module: MSSP
In SPI Slave mode with slave select enabled
(SSPM<3:0> = 0100), the minimum time between
the falling edge of the SS pin and first SCK edge
is greater than specified in parameter 70 in
Table 28-17 and Table 28-18. The updated
specification is shown in bold in Table 3.
The minimum time between SS
pin low and an
SSPBUF write is also 3 T
CY. If the falling edge of
the SS
pin occurs greater than 3 TCY, before the
first SCK edge or loading SSPBUF, the peripheral
will function correctly. Also, if SSPBUF is written
prior to the SS
pin going low, the peripheral will
function correctly.
TABLE 3: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING)
Work around
None.
Affected Silicon Revisions
A3 B4 B5 B6 B7
XXX
I
2
C Master mode, clock
F
OSC
4 SSPADD 1+()•
----------------------------------------------=
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
↓ to SCK ↓ or SCK ↑ Input 3TCY —ns
A3 B4 B5 B6 B7
XXX
X