Information

© 2009 Microchip Technology Inc. DS80478A-page 13
PIC18F2455/2550/4455/4550
26. Module: MSSP
With MSSP in SPI Master mode, FOSC/64 or
Timer2/2 clock rate and CKE = 0, a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit (SSPIF) is set or
the Buffer Full bit (BF) is set – before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents.
Affected Silicon Revisions
27. Module: MSSP
In an I
2
C system with multiple slave nodes, an
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and SSPOV bits. In both
situations, the SSPIF bit is not set and an interrupt
will not occur. The device will vector to the Interrupt
Service Routine only if the interrupt is enabled and
an address match occurs.
Work around
The I
2
C slave must clear the SSPOV bit after each
I
2
C event to maintain normal operation.
Affected Silicon Revisions
28. Module: EUSART
The EUSART auto-baud feature may periodically
measure the incoming baud rate incorrectly. The
rate of incorrect baud-rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Affected Silicon Revisions
29. Module: A/D
When the A/D clock source is selected as 2 TOSC
or RC (when ADCS<2:0> = 000 or x11), in
extremely rare cases, the E
IL (Integral Linearity
Error) and E
DL (Differential Linearity Error) may
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select a different A/D clock source (4 TOSC,
8T
OSC, 16 TOSC, 32 TOSC, 64 TOSC) and avoid
selecting the 2 T
OSC or RC modes.
Affected Silicon Revisions
30. Module: Resets (BOR)
If either the HLVD or USB modules are enabled,
clearing the SBOREN bit (RCON<6>) when the soft-
ware controlled BOR feature is enabled
(BOREN<1:0> = 01) may cause a Brown-out Reset
(BOR) event.
Work around
Before clearing the SBOREN bit, temporarily
disable the HLVD and USB modules.
Affected Silicon Revisions
A3 B4 B5 B6 B7
XXXX
X
A3 B4 B5 B6
B7
X
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
XXX
A3 B4 B5 B6 B7
X