Information

PIC18F2455/2550/4455/4550
DS80478A-page 12 © 2009 Microchip Technology Inc.
22. Module: EUSART
With the auto-wake-up option enabled by setting
the WUE bit (BAUDCON<1>), the RCIF
(PIR1<5>) bit will become set on a high-to-low
transition on the RX pin. However, the WUE bit
may not clear within 1 T
CY of a low-to-high
transition on RX.
While the WUE bit is set, reading the Receive Buf-
fer (RCREG) will not clear the RCIF interrupt flag.
Therefore, the first opportunity to automatically
clear RCIF by reading RCREG may take longer
than expected.
Work around
Either of these work arounds can be used:
• Clear the WUE bit in software, after the wake-
up event has occurred and prior to reading the
receive buffer (RCREG)
• Poll the WUE bit and read RCREG, after the
WUE bit is automatically cleared
Affected Silicon Revisions
23. Module: Timer1/3
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH
registers. The timers increment and set the
interrupt flags as expected. The timer registers can
also be written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
(T1CON<7>).
2. Use the internal clock synchronization option
by clearing the T1SYNC
bit (T1CON<2>).
Affected Silicon Revisions
24. Module: Reset
The indicated version of silicon does not support
the functionality described in Note 1 of
parameter D002 in Section 28.1 “DC Character-
istics: Supply Voltage” of the data sheet. The
RAM content may be altered during a Reset event
if the following conditions are met.
• Device is accessing RAM
• Asynchronous Reset (WDT, BOR or MCLR
)
occurs when a write operation is being
executed (start of a Q4 cycle) or if a RESET
instruction is executed and immediately
followed by a RETURN instruction
Work around
None.
Affected Silicon Revisions
25. Module: ECCP (PWM Mode)
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM
output may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• A non-zero dead-band delay is specified
(PDC<6:0> > 0)
• The duty cycle has a value of 0 through 3, or
4n + 3 (n ≥ 1)
Work around
None.
Affected Silicon Revisions
Note: RCIF can only be cleared by reading
RCREG.
A3 B4 B5 B6
B7
X
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
XXXX
X