Information

© 2009 Microchip Technology Inc. DS80478A-page 11
PIC18F2455/2550/4455/4550
19. Module: EUSART
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREG, are trans-
ferred to the TSR during the transmission of a Stop
bit. For this to occur, three things must happen in
the same instruction cycle:
• TXREG is written to
• The baud rate counter overflows (at the end of
the bit period)
• A Stop bit is being transmitted (shifted out of
TSR)
Work around
If possible, do not use the module’s double-buffer
capability. Instead, load the TXREG register when
the TRMT bit (TXSTA<1>) is set, indicating the
TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, load TXREG immedi-
ately after TXIF is set, or wait 1 bit time after TXIF
is set. Both solutions prevent writing TXREG while
a Stop bit is transmitted. The TXIF bit is set at the
beginning of the Stop bit transmission.
If transmission is intermittent, do one of the
following:
• Wait for the TRMT bit to be set before loading
TXREG
• Use a free timer resource to time the baud
period.
Set up the timer to overflow at the end of a
Stop bit, then start the timer when you load the
TXREG. Do not load the TXREG when timer
is about to overflow.
Affected Silicon Revisions
20. Module: EUSART
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTA<0>) is not modified immediately after the
RCIDL bit (BAUDCON<6>) is set.
Work around
Write to TX9D only when a reception is not in
progress (RCIDL = 1). Since there is no interrupt
associated with RCIDL, it must be polled in
software to determine when TX9D can be
updated.
Affected Silicon Revisions
21. Module: EUSART
After the last received byte has been read from the
EUSART receive buffer (RCREG), the value is no
longer valid for subsequent read operations.
Work around
The RCREG register should only be read once for
each byte received. After each byte is received
from the EUSART, store the byte in a user
variable.
To determine when a byte is available to read from
RCREG, poll the RCIDL bit (BAUDCON<6>) for a
low-to-high transition, or use the EUSART Receive
Interrupt Flag, RCIF (PIR1<5>).
Affected Silicon Revisions
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X