Information

PIC18F2455/2550/4455/4550
DS80478A-page 10 © 2009 Microchip Technology Inc.
17. Module: MSSP
It has been observed that following a Power-on
Reset, the I
2
C mode may not initialize properly by
just configuring the SCL and SDA pins as either
inputs or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application's power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
2
C operation:
1. Configure the SCL and SDA pins as outputs by
clearing their corresponding TRIS bits.
2. Force SCL and SDA low by clearing the
corresponding LAT bits.
3. While keeping the LAT bits clear, configure
SCL and SDA as inputs by setting their TRIS
bits.
Once this is done, use the SSPCON1 and
SSPCON2 registers to configure the proper I
2
C
mode as before.
Affected Silicon Revisions
18. Module: MSSP
When the MSSP is configured for SPI mode, the
Buffer Full bit, BF (SSPSTAT<0>), should not be
polled in software to determine when the transfer
is complete.
Work around
Copy the SSPSTAT register into a variable and
perform the bit test on the variable. In Example 5,
SSPSTAT is copied into the working register
where the bit test is performed.
EXAMPLE 5: SSPSTAT WORK AROUND
A second option is to poll the Master Synchronous
Serial Port Interrupt Flag bit, SSPIF (PIR1<3>).
This bit can be polled and will set when the transfer
is complete.
Affected Silicon Revisions
A3 B4 B5 B6 B7
X
A3 B4 B5 B6 B7
X
loop_MSB:
MOVF SSPSTAT, W
BTFSS WREG, BF
BRA loop_MSB