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PIC18F2455/2550/4455/4550

The PIC18F2455/2550/4455/4550 family devices that

you have received conform functionally to the current

Device Data Sheet (DS39632D), except for the anoma-

lies described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC18F2455/2550/4455/4550

silicon.

Data Sheet clarifications and corrections start on page 18,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

onfigure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger

>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger

>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC18F2455/2550/

4455/4550 silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon revision

(B7).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A3 B4 B5 B6 B7

PIC18F2455 126Xh

2h 4h 5h 6h 7h

PIC18F2550 124Xh

PIC18F4455 122Xh

PIC18F4550 120Xh

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC18F2XXX/4XXX Family Flash Microcontroller Programming Specification” (DS39622) for

detailed information on Device and Revision IDs for your specific device.

PIC18F2455/2550/4455/4550 Family

Silicon Errata and Data Sheet Clarification

Summary of content (26 pages)

PAGE 1
PIC18F2455/2550/4455/4550 PIC18F2455/2550/4455/4550 Family Silicon Errata and Data Sheet Clarification The PIC18F2455/2550/4455/4550 family devices that you have received conform functionally to the current Device Data Sheet (DS39632D), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ 3: 1.
PAGE 2
PIC18F2455/2550/4455/4550 TABLE 2: SILICON ISSUE SUMMARY Module Item Number Feature Affected Revisions(1) Issue Summary A3 EUSART Nine-Bit mode 1. Back-to-back timing transmit corruption X Timer1/3 Sixteen-Bit mode 2. Write to TMR1H/3H may lengthen duration X MSSP Slave Transmit 3. Slave transmit, 10 TCY not blocked X Interrupts Two-Cycle Instructions 4. Special considerations for interrupt context save X ECCP ECCPASE Bit 5.
PAGE 3
PIC18F2455/2550/4455/4550 TABLE 2: Module SILICON ISSUE SUMMARY (CONTINUED) Feature Affected Revisions(1) Item Number Issue Summary A3 B4 B5 B6 B7 X X X X X X X BOR HLVD or USB 30. Clearing SBOREN can cause BOR X MSSP I2C mode 31. I2C baud rate not meeting formula X MSSP SPI slave 32. SPI slave not meeting timing parameter 70 X Timer1/3 Eight-Bit Async 33. Need delay between consecutive writes X BOR Threshold 34.
PAGE 4
PIC18F2455/2550/4455/4550 3. Module: MSSP Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B7). 1. Module: EUSART In Slave Transmit mode, when a transmission is initiated, the SSPBUF register may be written for up to 10 TCY before additional writes are blocked.
PAGE 5
PIC18F2455/2550/4455/4550 4. Module: Interrupts If an interrupt occurs during a two-cycle instruction that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register and upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register.
PAGE 6
PIC18F2455/2550/4455/4550 C Programming Language The exact work around depends on the compiler in use. Please refer to your C compiler documentation for details. If using the Microchip MPLAB® C18 C Compiler, define both high and low-priority interrupt handler functions as “low priority” by using the pragma interruptlow directive. This directive instructs the compiler to not use the EXAMPLE 2: RETFIE FAST instruction.
PAGE 7
PIC18F2455/2550/4455/4550 5. Module: ECCP 7. Module: ECCP When monitoring a shutdown condition using a bit test on the ECCPASE bit (ECCP1AS<7>) or performing a bit operation on the ECCPASE bit, the device may produce unexpected results. Work around Before performing a bit test or bit operation on the ECCPASE bit, copy the ECCP1AS register to the working register and perform the operation there. By avoiding these operations on the ECCPASE bit in the ECCP1AS register, the module will operate normally.
PAGE 8
PIC18F2455/2550/4455/4550 8. Module: A/D • Configure the A/D to use the VREF+ and VREFpins for the voltage references. This is done by setting the VCFG<1:0> bits (ADCON1<5:4>). • Perform a conversion on a known voltage reference voltage and adjust the A/D result in software. • Increase system clock speed to 48 MHz and adjust A/D settings accordingly. Higher system clock frequencies decrease offset error. The A/D offset is greater than the specified limit in Table 28-8 of the Device Data Sheet.
PAGE 9
PIC18F2455/2550/4455/4550 11. Module: PORTD 14. Module: USB Each of the PORTD pins has a weak internal pull-up. A single control bit, RDPU (PORTE<7>), can turn on all the pull-ups. After the pull-up has been enabled (PORTE<7> = 1), any access to the PORTE register would cause the RDPU control bit to clear, except those accesses that write a '1' to PORTE<7>. The Ping-Pong Buffer mode in which the ping-pong buffers are enabled for Endpoints 1 to 15 (UCFG (PPB<1:0) = 11) is not supported.
PAGE 10
PIC18F2455/2550/4455/4550 17. Module: MSSP 18. Module: MSSP It has been observed that following a Power-on Reset, the I2C mode may not initialize properly by just configuring the SCL and SDA pins as either inputs or outputs. This has only been seen in a few unique system environments. A test of a statistically significant sample of preproduction systems, across the voltage and current range of the application's power supply, should indicate if a system is susceptible to this issue.
PAGE 11
PIC18F2455/2550/4455/4550 19. Module: EUSART 20. Module: EUSART In rare situations, one or more extra zero bytes have been observed in a packet transmitted by the module operating in Asynchronous mode. The actual data is not lost or corrupted; only unwanted (extra) zero bytes are observed in the packet. This situation has only been observed when the contents of the transmit buffer, TXREG, are transferred to the TSR during the transmission of a Stop bit.
PAGE 12
PIC18F2455/2550/4455/4550 22. Module: EUSART 24. Module: Reset With the auto-wake-up option enabled by setting the WUE bit (BAUDCON<1>), the RCIF (PIR1<5>) bit will become set on a high-to-low transition on the RX pin. However, the WUE bit may not clear within 1 TCY of a low-to-high transition on RX. The indicated version of silicon does not support the functionality described in Note 1 of parameter D002 in Section 28.1 “DC Characteristics: Supply Voltage” of the data sheet.
PAGE 13
PIC18F2455/2550/4455/4550 26. Module: MSSP 28. Module: EUSART With MSSP in SPI Master mode, FOSC/64 or Timer2/2 clock rate and CKE = 0, a write collision may occur if SSPBUF is loaded immediately after the transfer is complete. A delay may be required after the MSSP Interrupt Flag bit (SSPIF) is set or the Buffer Full bit (BF) is set – before writing SSPBUF. If the delay is insufficiently short, a write collision may occur as indicated by the WCOL bit being set.
PAGE 14
PIC18F2455/2550/4455/4550 31. Module: MSSP 32. Module: MSSP When operated in I2C™ Master mode, the I2C baud rate may be somewhat slower than predicted by the following formula: F OSC 2 I C Master mode, clock = ---------------------------------------------4 • ( SSPADD + 1 ) Work around If the target application is sensitive to the baud rate and requires more precision, the SSPADD value can be adjusted to compensate.
PAGE 15
PIC18F2455/2550/4455/4550 33. Module: Timer1/3 35. Module: Resets (BOR) For Timer1 or Timer3, if the TMRxH and TMRxL registers are written to in consecutive instruction cycles, the timer may not be updated with the correct value if it is configured for externally clocked, 8-Bit Asynchronous mode (T1CON<7:0> or T3CON<7:0> = 0xxx x111). For the purposes of this issue, instructions that directly affect the contents of the Timer registers are considered to be writes.
PAGE 16
PIC18F2455/2550/4455/4550 38. Module: MSSP If the application firmware is expecting to receive valid data, in either SPI Slave or Master mode, the firmware must read from the SSPBUF register before writing the next byte to transmit to SSPBUF. If the firmware does not read from SSPBUF, the BF bit (SSPSTAT<0>) can still be set from the previous transaction. If the BF bit is set, the incoming data byte is blocked from transferring from the SSPSR Shift register to the SSPBUF register.
PAGE 17
PIC18F2455/2550/4455/4550 39. Module: MSSP (I2C™ Slave) 40. Module: MSSP (I2C™ Master) When configured for I2C™ slave reception, the MSSP module may not receive the correct data, in extremely rare cases. This occurs only if the Serial Receive/Transmit Buffer Register (SSPBUF) is not read after the SSPIF interrupt (PIR1<3>) has occurred, but before the first rising clock edge of the next byte being received.
PAGE 18
PIC18F2455/2550/4455/4550 1. Module: Timer1 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39632D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. EXAMPLE 12-1: The Real-Time Clock application example, cited in Section 12.6 “Using Timer1 as a Real-Time Clock,” has changed. Example 12-1 is corrected to the following example.
PAGE 19
PIC18F2455/2550/4455/4550 2. Module: Timer1 The following text, Section 12.7 “Considerations in Asynchronous Counter Mode”, is new. It defines the proper method to update the TMR1 registers in Asynchronous mode. Section 12.7 is located after Section 12.6 “Using Timer1 as a Real-Time Clock” in the data sheet. 12.
PAGE 20
PIC18F2455/2550/4455/4550 7. Module: Electrical Characteristics In Section 28.3 “DC Characteristics,” pinspecific variations of parameters, D031 (Input Low Voltage) and D041 (Input High Voltage), are corrected as characteristic for pins, RB0 and RB1, not pins, RC3 and RC4. The following relevant portion of the table indicates the corrections. (For clarity, the corrected items appear in bold text – all other text appears in plain text for purposes of this errata.) 28.
PAGE 21
PIC18F2455/2550/4455/4550 9. Module: Electrical Characteristics In Table 28-5, parameter D323 (Regulator Voltage Output) is qualified with the condition of a minimum device VDD ≥ 4.0V in the Comments column. The following relevant portion of Table 28-1 indicates the correction. (For clarity, the corrected item appears in bold text – all other text has been changed to plain text for purposes of this errata.
PAGE 22
PIC18F2455/2550/4455/4550 10. Module: MSSP (SPI Master) In Section 19.3.5, “Master Mode,” the following content is added: When used in Timer2 Output/2 mode, the SPI bit rate can be configured using the PR2 Period register and the Timer2 prescaler. To operate in this mode, firmware must first initialize and enable the Timer2 module before it can be used with the MSSP. Once enabled, the Timer2 module is free-running and mostly independent of the MSSP module.
PAGE 23
PIC18F2455/2550/4455/4550 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (7/2009) Initial release of this new, combined document. Republished earlier silicon issues from documents being discontinued (listed below). Added new silicon issues 39 (MSSP, I2C Slave), 40 (MSSP, I2C Master) and 41 (EUSART). Republished earlier data sheet clarifications from data sheet errata being discontinued. Added new data sheet issue 10 (MSSP, SPI Master).
PAGE 25
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 26
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