Information

© 2008 Microchip Technology Inc. DS80209H-page 9
PIC18F2420/2520/4420/4520
24. Module: EUSART
The EUSART auto-baud feature may periodically
measure the incoming baud rate incorrectly. The
rate of incorrect baud rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
25. Module: EUSART
In Synchronous mode (SYNC = 1) with clock
polarity high (SCKP = 1), the EUSART transmits a
shorter than expected clock on the CK pin for bit 0.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
26. Module: EUSART
In Synchronous mode, EUSART baud rates using
SPBRG values of ‘0’ and ‘1’ may not function
correctly.
Work around
Use another baud rate configuration to generate
the desired baud rate.
Date Codes that pertain to this issue:
All engineering and production devices.
27. Module: MSSP
In an I
2
C™ system with multiple slave nodes, an
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit and load
SSPBUF. The second occurrence will set the
SSPOV bit and the I
2
C slave will stop responding
to I
2
C activity.
In both occurrences, no NACK bit is sent; the
SSPIF bit is not set and no interrupt will occur.
Work around
The I
2
C slave must periodically poll the BF flag
independently of SSPIF interrupts. If BF is set and
SSPIF is clear, retest BF to ensure that an interrupt
was not just processed. If BF is still set, the slave
should read SSPBUF and clear SSPOV. Discard
the data from SSPBUF.
Date Codes that pertain to this issue:
All engineering and production devices.
28. Module: MSSP
In I
2
C Master mode, the BRG value of ‘0’ may not
work correctly.
Work around
Use a BRG value greater than ‘0’ by setting
SSPADD ≥ 1.
Date Codes that pertain to this issue:
All engineering and production devices.
29. Module: MSSP
In I
2
C Master mode, the RCEN bit is set by soft-
ware to begin data reception and cleared by the
peripheral after a byte is received. After a byte is
received, the device may take up to 80 T
CY to clear
RCEN and 800 T
CY when using MPLAB
®
ICD 2
and MPLAB ICE emulators.
Work around
Single byte receptions are typically not affected,
since the delay between byte receptions is
typically long enough for the RCEN bit to clear. For
multiple byte receptions, the software must wait
until the bit is cleared by the peripheral before the
next byte can be received.
Date Codes that pertain to this issue:
All engineering and production devices.
30. Module: MSSP
Setting the SEN bit initiates a Start sequence on
the bus, after which, the SEN bit is cleared auto-
matically by hardware. If the SEN bit is set again
(without an address byte being transmitted), a
Start sequence will not commence and the SEN bit
will not be cleared. This condition causes the bus
to remain in an active state. The system is Idle
when ACKEN, RCEN, PEN, RSEN and SEN are
clear.
Work around
Set the PEN or RSEN bit to transmit a Stop or
Repeated Start sequence, although the SEN bit
may still be set, indicating the bus is active. After
the sequence has completed, the PEN, RSEN and
SEN bit will be clear, indicating the bus is Idle.
Clearing and setting the SSPEN bit will also reset
the I
2
C peripheral and clear the PEN, RSEN and
SEN status bits.
Date Codes that pertain to this issue:
All engineering and production devices.