Information

PIC18F2420/2520/4420/4520
DS80209H-page 12 © 2008 Microchip Technology Inc.
39. Module: MSSP
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
40. Module: MSSP
When the MSSP is configured for SPI mode, the
Buffer Full bit, BF (SSPSTAT<0>), should not be
polled in software to determine when the transfer
is complete.
Work around
Copy the SSPSTAT register into a variable and
perform the bit test on the variable. In Example 5,
SSPSTAT is copied into the working register
where the bit test is performed.
EXAMPLE 5:
A second option is to poll the Master Synchronous
Serial Port Interrupt Flag bit, SSPIF (PIR1<3>).
This bit can be polled and will set when the transfer
is complete.
Date Codes that pertain to this issue:
All engineering and production devices.
41. Module: Timer1
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH regis-
ters. The timers increment and set the interrupt
flags as expected. The timer registers can also be
written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
(T1CON<7>).
2. Use the internal clock synchronization option
by clearing the T1SYNC
bit (T1CON<2>).
Date Codes that pertain to this issue:
All engineering and production devices.
42. Module: Reset
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 26.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or
MCLR) occurs when a write operation is being
executed (start of a Q4 cycle).
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
43. Module: 10-Bit Analog-to-Digital
Converter
When the AD clock source is selected as 2 TOSC or
RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the EIL (Integral Linearity
Error) and E
DL (Differential Linearity Error) may
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select the AD clock source as 4 TOSC, 8 TOSC,
16 T
OSC, 32 TOSC or 64 TOSC and avoid selecting
2T
OSC or RC.
Date Codes that pertain to this issue:
All engineering and production devices.
loop_MSB:
MOVF SSPSTAT, W
BTFSS WREG, BF
BRA loop_MSB