Information

© 2008 Microchip Technology Inc. DS80209H-page 11
PIC18F2420/2520/4420/4520
34. Module: EUSART
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTA<0>) is not modified immediately after the
RCIDL bit (BAUDCON<6>) is set.
Work around
Write to TX9D only when a reception is not in
progress (RCIDL = 1). Since there is no interrupt
associated with RCIDL, it must be polled in
software to determine when TX9D can be
updated.
Date Codes that pertain to this issue:
All engineering and production devices.
35. Module: EUSART
After the last received byte has been read from the
EUSART receive buffer, RCREG, the value is no
longer valid for subsequent read operations.
Work around
The RCREG register should only be read once for
each byte received. After each byte is received
from the EUSART, store the byte into a user vari-
able. To determine when a byte is available to read
from RCREG, poll the RCIDL bit (BAUDCON<6>)
for a low-to-high transition, or use the EUSART
Receive Interrupt Flag, RCIF (PIR1<5>).
Date Codes that pertain to this issue:
All engineering and production devices.
36. Module: EUSART
With the auto-wake-up option enabled by setting
the WUE (BAUDCON<1>) bit, the RCIF
(PIR1<5>) bit will become set on a high-to-low
transition on the RX pin. However, the WUE bit
may not clear within 1 T
CY of a low-to-high transi-
tion on RX. While the WUE bit is set, reading the
receive buffer, RCREG, will not clear the RCIF
interrupt flag. Therefore, the first opportunity to
automatically clear RCIF by reading RCREG may
take longer than expected.
Work around
There are two work arounds available:
1. Clear the WUE bit in software after the wake-
up event has occurred prior to reading the
receive buffer, RCREG.
2. Poll the WUE bit and read RCREG after the
WUE bit is automatically cleared.
Date Codes that pertain to this issue:
All engineering and production devices.
37. Module: MSSP
The MSSP configured in SPI Slave mode will
generate a write collision if SSPBUF is updated and
the previous SSPBUF contents have not been
transferred
to the shift register.
Re-initializing the MSSP by clearing and setting the
SSPEN (SSPCON1<5>) bit prior to rewriting
SSPBUF will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify whether the previous contents were
transferred by reading the BF (SSPSTAT<0>) bit. If
the previous byte has not been transferred, update
SSPBUF and clear the WCOL (SSPCON1<7>) bit if
necessary.
Date Codes that pertain to this issue:
All engineering and production devices.
38. Module: MSSP
It has been observed that following a Power-on
Reset, I
2
C mode may not initialize properly by just
configuring the SCL and SDA pins as either inputs
or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application's power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
2
C operation:
1. Configure the SCL and SDA pins as outputs by
clearing their corresponding TRIS bits.
2. Force SCL and SDA low by clearing the
corresponding LAT bits.
3. While keeping the LAT bits clear, configure
SCL and SDA as inputs by setting their TRIS
bits.
Once this is done, use the SSPCON1 and
SSPCON2 registers to configure the proper I
2
C
mode as before.
Date Codes that pertain to this issue:
All engineering and production devices.
Note: RCIF can only be cleared by reading
RCREG