Information

PIC18F2420/2520/4420/4520

DS80304D-page 4  2009 Microchip Technology Inc.

6. Module: Master Synchronous Serial Port

(MSSP)

When configured for I

C™ slave reception, the

MSSP module may not receive the correct data, in

extremely rare cases. This occurs only if the Serial

Receive/Transmit Buffer Register (SSPBUF) is not

read after the SSPIF interrupt (PIR1<3>) has

occurred, but before the first rising clock edge of

the next byte being received.

Work around

The issue can be resolved in either of these ways:

• Prior to the I

C slave reception, enable the

clock stretching feature.

This is done by setting the SEN bit

(SSPCON2<0>).

• Each time the SSPIF is set, read the SSPBUF

before the first rising clock edge of the next byte

being received.

Date Codes that pertain to this issue:

All engineering and production devices.

REVISION HISTORY

Rev A Document (2/2007)

First revision of this document. Silicon issue 1 (MSSP)

and 2 (MSSP [SPI Master] ).

Rev B Document (

4/2007)

Added silicon issue 3 (Enhanced Universal

Synchronous Receiver Transmitter – EUSART).

Rev C Document (6/2007)

Added silicon issue 4 (10-Bit Analog-to-Digital

Converter).

Rev D Document (8/2009)

Added silicon issues 5 (EUSART) and 6 (MSSP).