Information

 2009 Microchip Technology Inc. DS80304D-page 3
PIC18F2420/2520/4420/4520
4. Module: 10-Bit Analog-to-Digital
Converter
When the AD clock source is selected as 2 TOSC or
RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the EIL (Integral Linearity
Error) and E
DL (Differential Linearity Error) may
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select the AD clock source as 4 TOSC, 8 TOSC,
16 T
OSC, 32 TOSC or 64 TOSC and avoid selecting
2T
OSC or RC.
Date Codes that pertain to this issue:
All engineering and production devices.
5. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTA <7>, = 0)
• The EUSART is re-enabled (RCSTA <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2-TCY delay after re-enabling the EUSART.
1. Disable Receive Interrupts (RCIE bit,
PIE1<5>, = 0).
2. Disable the EUSART (RCSTA <7>, = 0).
3. Re-enable the EUSART (RCSTA <7> = 1).
4. Re-enable Receive Interrupts (PIE1<5> = 1).
(This is the first T
CY delay.)
5. Execute an NOP instruction.
(This is the second T
CY delay.)
Date Codes that pertain to this issue:
All engineering and production devices.
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin with the interrupt generated on the falling edge; bit
cleared in hardware on following rising edge
0 = RX pin is not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER (CONTINUED)