Information

PIC18F2420/2520/4420/4520
DS80363C-page 4  2009 Microchip Technology Inc.
7. Module: Resets (BOR)
An unexpected Reset may occur if the Brown-out
Reset module (BOR) is disabled, and then re-
enabled, when the High/Low-Voltage Detection
module (HLVD) is not enabled (HLVDCON<4> = 0).
This issue affects BOR modes: BOREN<1:0> = 10
and BOREN<1:0> = 01. In both of these modes, if
the BOR module is re-enabled while the device is
active, unexpected Resets may be generated.
Work around
If BOR is required, and power consumption is not
an issue, use BOREN<1:0> = 11. For
BOREN<1:0> = 10 mode, either switch to
BOREN<1:0> = 11 mode or enable the HLVD
(HLVDCON<4> = 1) prior to entering Sleep.
If power consumption is an issue and low power is
desired, Microchip does not recommend using
BOREN<1:0> = 10 mode. Instead, use
BOREN<1:0> = 01 and follow the steps below
when entering and exiting Sleep.
1. Disable BOR by clearing SBOREN
(RCON<6> = 0).
2. Enter Sleep mode (if desired).
3. After exiting Sleep mode, enable the HLVD
(HLVDCON<4> = 1).
4. Wait for the internal reference voltage (T
IRVST)
to stabilize (typically 20 s).
5. Re-enable BOR by setting SBOREN
(RCON<6> = 1).
6. Disable the HLVD by clearing HLVDEN
(HLVDCON<4> = 0).
Date Codes that pertain to this issue:
All engineering and production devices.
8. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTA <7>, = 0)
• The EUSART is re-enabled (RCSTA <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2-TCY delay after re-enabling the EUSART.
1. Disable Receive Interrupts (RCIE bit,
PIE1<5>, = 0).
2. Disable the EUSART (RCSTA <7>, = 0).
3. Re-enable the EUSART (RCSTA <7> = 1).
4. Re-enable Receive Interrupts (PIE1<5> = 1).
(This is the first TCY delay.)
5. Execute a NOP instruction.
(This is the second T
CY delay.)
Date Codes that pertain to this issue:
All engineering and production devices.
9. Module: Master Synchronous Serial Port
(MSSP)
When configured for I
2
C™ slave reception, the
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read after the SSPIF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPCON2<0>).
• Each time the SSPIF is set, read the SSPBUF
before the first rising clock edge of the next byte
being received.
Date Codes that pertain to this issue:
All engineering and production devices.