Information

© 2007 Microchip Technology Inc. DS80288G-page 3
PIC18F2420/2520/4420/4520
6. Module: Enhanced Universal
Synchronous Receiver
Transmitter (EUSART)
One bit has been added to the BAUDCON register
and one bit has been renamed. The added bit is
RXDTP and is in the location, BAUDCON<5>. The
renamed bit is the TXCKP bit (BAUDCON<4>),
which had been named SCKP.
The TXCKP (BAUDCON<4>) and RXDTP
(BAUDCON<5>) bits enable the Synchronous
mode TX and RX signals to be inverted (polarity
reversed). RXDTP has no effect on the
Synchronous mode DT signal.
Register 18-3, on page 204, will be changed as
shown.
Work around
None required.
Date Codes that pertain to this issue:
All engineering and production devices.
REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit
1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode
(must be cleared in software)
0 = No BRG rollover has occurred
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is Active
bit 5 RXDTP: Receive Data Polarity Select bit (Asynchronous mode only)
Asynchronous mode:
1 = Receive data (RX) is inverted. Idle state is a low level.
0 = No inversion of receive data (RX). Idle state is a high level.
bit 4 TXCKP: Transmit/Clock Polarity Select bit
Asynchronous mode:
1 = Transmit data (TX) is inverted. Idle state is a low level.
0 = No inversion of transmit data (TX). Idle state is a high level.
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3 BRG16: 16-bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG
0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode); SPBRGH value ignored
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin with the interrupt generated on the falling edge; bit
cleared in hardware on following rising edge
0 = RX pin is not monitored or rising edge detected
Synchronous mode:
Unused in this mode.