Information

© 2009 Microchip Technology Inc. DS80244D-page 3
PIC18F1220/1320
Clarifications/Corrections to the Data
Sheet
In the PIC18F1220/1320 Device Data Sheet
(DS39605F), the following clarifications and corrections
should be noted:
1. Module: Timer3 (Special Event Trigger)
In Section 14.0 “Timer3 Module”, bit 6 of the
T3CON register was incorrectly defined as
unimplemented. The correct definition for
T3CON<6> is T3CCP2 and is shown in bold
below:
In all tables and references to the T3CON register
throughout the document, T3CON<6> should
always be interpreted as the control bit, T3CCP2,
and not as an unimplemented bit position.
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
2. Module: Data EEPROM
In Table 22-1 on page 254 of the Device Data
Sheet, the typical value for parameter D122, Data
EEPROM Erase/Write Cycle Time (T
DEW) has
changed. The new value is 5.5 ms and is shown in
bold below.
TABLE 22-1: MEMORY PROGRAMMING REQUIREMENTS
3. Module: Oscillator Configurations
The INTOSC clock source has been modified to
reduce its start-up time, and to improve its
frequency stability.
The IOFS bit (OSCCON<2>) will indicate the
INTOSC has settled in approximately 128 μs.
The INTOSC clock frequency is adjusted using the
TUN<5:1> bits (OSCTUNE<5:1>). The TUN0 bit
(OSCTUNE<0>) is no longer effective in adjusting
the INTOSC frequency, although it continues to be
readable and writable.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON
bit 7 bit 0
bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCP1 Enable bits
1x = Timer3 is the clock source for compare/capture CCP module
01 = Reserved
00 = Timer1 is the clock source for compare/capture CCP module
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ T
A ≤ +85°C for industrial
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
D122 T
DEW Erase/Write Cycle Time — 5.5 —ms