Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 18 8-Bit 40 MHz I/O number 16

PIC18F1220/1320

The PIC18F1220/1320 Rev. D0 parts you have

received conform functionally to the Device Data Sheet

(DS39605F), except for the anomalies described

below.

All of the issues listed here will be addressed in future

revisions of the PIC18F1220/1320 silicon.

The following silicon errata apply only to

PIC18F1220/1320 devices with these Device/

Revision IDs:

1. Module: Core (DAW Instruction)

The DAW instruction may improperly clear the

Carry bit (STATUS<0>) when executed.

Work around

Test the Carry bit state before executing the DAW

instruction. If the Carry bit is set, increment the

next higher byte to be added, using an instruction

such as INCFSZ (this instruction does not affect

any Status flags and will not overflow a BCD nib-

ble). After the DAW instruction has been executed,

process the Carry bit normally (see Example 1).

EXAMPLE 1: PROCESSING THE CARRY

BIT DURING BCD ADDITIONS

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: EUSART

The auto-baud measurement may not determine

the correct baud rate if the ABDEN bit is set while

the RB4/RX pin is low.

Work around

If the wake-up function is being used (WUE is set),

wait for the RB4/RX pin to go high following a

Break signal before setting the ABDEN bit.

If the wake-up function is not being used, ensure

that RB4/RX is Idle (high between bytes) before

setting the ABDEN bit.

Date Codes that pertain to this issue:

All engineering and production devices.

3. Module: Reset

It has been observed that in certain Reset condi-

tions, including power-up, the first GOTO instruction

at address 0x0000 may not be executed. This

occurrence is rare and affects very few applications.

To determine if your system is affected, test a

statistically significant number of applications across

the operating temperature, voltage and frequency

ranges of the application. Affected systems will

repeatably fail normal testing. Systems not affected

will continue to not be affected over time.

Work around

Insert a NOP instruction at address 0x0000.

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F1220 0000 0111 111 0 0111

PIC18F1320 0000 0111 110 0 0111

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

MOVLW 0x80 ; .80 (BCD)

ADDLW 0x80 ; .80 (BCD)

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

DAW

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

This is repeated for each DAW instruction.

PIC18F1220/1320 Rev. D0 Silicon/Data Sheet Errata

Summary of content (10 pages)

PAGE 1
PIC18F1220/1320 PIC18F1220/1320 Rev. D0 Silicon/Data Sheet Errata The PIC18F1220/1320 Rev. D0 parts you have received conform functionally to the Device Data Sheet (DS39605F), except for the anomalies described below. All of the issues listed here will be addressed in future revisions of the PIC18F1220/1320 silicon. The following silicon errata apply only to PIC18F1220/1320 devices with these Device/ Revision IDs: 2.
PAGE 2
PIC18F1220/1320 4. Module: Oscillator (INTOSC) The Least Significant bit of the OSCTUNE register, TUN0 (OSCTUNE<0>), is not implemented. As a result, incrementing or decrementing the OSCTUNE register will not have the expected single-step change on the frequency of INTOSC. This is expected to be a permanent design change for the device. Work around For incremental changes to OSCTUNE, copy its contents to WREG, increment or decrement WREG twice, then write WREG back to OSCTUNE.
PAGE 3
PIC18F1220/1320 Clarifications/Corrections to the Data Sheet In the PIC18F1220/1320 Device Data Sheet (DS39605F), the following clarifications and corrections should be noted: 1. Module: Timer3 (Special Event Trigger) In Section 14.0 “Timer3 Module”, bit 6 of the T3CON register was incorrectly defined as unimplemented.
PAGE 4
PIC18F1220/1320 4. Module: Oscillator Configurations 5. Module: DC Characteristics The INTRC clock source has been modified to improve its frequency stability. Modifications have been made that have changed the typical values for parameters, D022A (Brownout Reset) and D022B (Low-Voltage Detect). The new values will change the ninth and last page of the table shown. The OSCTUNE register no longer affects the INTRC frequency. Peripherals that use the INTRC clock source are also affected (WDT and FSCM).
PAGE 5
PIC18F1220/1320 6. Module: DC Characteristics The operating values for the SEC_RUN and SEC_IDLE modes are corrected, on the seventh and eighth pages of the nine-page table in Section 22.2 “DC Characteristics: Power-Down and Supply Current”. The new values are shown in bold text. 22.
PAGE 6
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PAGE 7
PIC18F1220/1320 REVISION HISTORY Rev A Document (08/2005) First revision of this document. Includes silicon issues 1 (Core), 2 (EUSART), 3 (Reset) and 4 (Oscillator (INTOSC Source)), and Data Sheet Clarification issues 1 (Timer3 (Special Event Trigger)) and 2 (Data EEPROM). Rev B Document (03/2006) Removed previous silicon issue 4 and added new silicon issues 4 (Oscillator/INTOSC) and 5 (Oscillator/INTRC). Data Sheet Clarification issue 1 (CCP) clarified as Timer3/Special Event Trigger.
PAGE 9
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 10
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.