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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 18 8-Bit 40 MHz I/O number 16

PIC18F1220/1320

The PIC18F1220/1320 Rev. B4 parts you have

received conform functionally to the Device Data Sheet

(DS39605C), except for the anomalies described

below.

All of the issues listed here will be addressed in future

revisions of the PIC18F1220/1320 silicon.

The following silicon errata apply only to

PIC18F1220/1320 devices with these Device/

Revision IDs:

1. Module: Core (DAW Instruction)

The DAW instruction may improperly clear the

Carry bit (STATUS<0>) when executed.

Work around

Test the Carry bit state before executing the DAW

instruction. If the Carry bit is set, increment the

next higher byte to be added, using an instruction

such as INCFSZ (this instruction does not affect

any Status flags and will not overflow a BCD nib-

ble). After the DAW instruction has been executed,

process the Carry bit normally (see Example 1).

EXAMPLE 1: PROCESSING THE CARRY

BIT DURING BCD ADDITIONS

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: EUSART

The auto-baud measurement may not determine

the correct baud rate if the ABDEN bit is set while

the RB4/RX pin is low.

Work around

If the wake-up function is being used (WUE is set),

wait for the RB4/RX pin to go high following a

Break signal before setting the ABDEN bit.

If the wake-up function is not being used, ensure

that RB4/RX is Idle (high between bytes) before

setting the ABDEN bit.

Date Codes that pertain to this issue:

All engineering and production devices.

3. Module: Data EEPROM

When writing to the data EEPROM, the contents of

the data EEPROM memory may not be written as

expected.

Work around

Either of two work arounds can be used:

1. Before beginning any writes to the data

EEPROM, enable the LVD (any voltage) and

wait for the internal voltage reference to

become stable. LVD interrupt requests may be

ignored. Once the LVD voltage reference is

stable, perform all EEPROM writes normally.

When writes have been completed, the LVD

may be disabled.

2. Configure the BOR as enabled (any voltage).

Select a threshold below V

DD to allow normal

operation. If V

DD is below the BOR threshold,

the device will be held in Brown-out Reset.

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F1220 00 0111 111 00100

PIC18F1320 00 0111 110 00100

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

MOVLW 0x80 ; .80 (BCD)

ADDLW 0x80 ; .80 (BCD)

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

DAW

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

This is repeated for each DAW instruction.

PIC18F1220/1320 Rev. B4 Silicon/Data Sheet Errata

Summary of content (6 pages)

PAGE 1
PIC18F1220/1320 PIC18F1220/1320 Rev. B4 Silicon/Data Sheet Errata The PIC18F1220/1320 Rev. B4 parts you have received conform functionally to the Device Data Sheet (DS39605C), except for the anomalies described below. All of the issues listed here will be addressed in future revisions of the PIC18F1220/1320 silicon. The following silicon errata apply only to PIC18F1220/1320 devices with these Device/ Revision IDs: 2.
PAGE 2
PIC18F1220/1320 4. Module: EUSART The auto-baud measurement may not determine the correct baud rate if the resulting measurement could overflow the SPBRG register when measuring slow baud rates. In such cases, SPBRGH:SPBRG will contain 0x00FF. Work around Either or both of the following work arounds may be used: 1. Use a faster baud rate that can not result in auto-baud measurements greater that 0x00FF. 2. Clear the BRGH bit (TXSTA<2>). This divides the bit clock by 64 rather than dividing it by 16. 5.
PAGE 3
PIC18F1220/1320 Clarifications/Corrections to the Data Sheet In the Device Data Sheet (DS39605C), the following clarifications and corrections should be noted. 1. Module: CCP In Section 14.0 “Timer3 Module”, bit 6 of the T3CON register was incorrectly defined as “unimplemented”.
PAGE 4
PIC18F1220/1320 REVISION HISTORY Rev A Document (12/2003) First revision of this document, silicon issues 1 (Core), 2 (EUSART) and 3 (Data EEPROM) and Data Sheet Clarification issues 1 (Internal RC Accuracy) and 2 (DC Characteristics Table). Rev B Document (2/2004) Added silicon issue 4 (EUSART). Added Data Sheet Clarification issue 3 (Timer1 Oscillator and In-Circuit Serial Programming). Rev C Document (4/2004) Added Data Sheet Clarification issues 4 Characteristics) and 5 (LVD Characteristics).
PAGE 5
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 6
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